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    Associative memory system with match,no match and multiple match resolution
    3.
    发明授权
    Associative memory system with match,no match and multiple match resolution 失效
    具有匹配，无匹配和多个匹配分辨率的相关记忆系统

    公开(公告)号：US3602899A

    公开(公告)日：1971-08-31

    申请号：US3602899D

    申请日：1969-06-20

    Applicant: IBM

    Inventor： LINDQUIST ARWIN B ,  PRICER WILBUR D ,  SEEBER ROBERT R

    IPC: G11C15/04 ,  G11C15/00

    CPC classification number: G11C15/04

    Abstract: An associative memory matrix having a writable portion made up of bistable memory cells and a read-only portion made up of monostable memory cells. The memory may be used as a conventional memory by placing an address in the address field of an entry register, masking out all other bits and performing a match interrogation with the unmasked bits. Since the contents of the address portion (read-only memory) of each stored word are unique, the interrogation results in a single match at the location containing the address sought. Included is a circuit for determining whether no match, one match, or a multiple match has occurred.

    10.
    发明专利
    未知

    公开(公告)号：DE1151959B

    公开(公告)日：1963-07-25

    申请号：DEJ0017995

    申请日：1960-04-20

    Applicant: IBM

    Inventor： LENTZ JOHN J ,  SEEBER ROBERT R

    IPC: G11C11/44 ,  G11C15/06

    Abstract: 931,057. Electrical digital data-storage apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. April 25, 1960 [April 30, 1959], No. 14352/60. Class 106 (1). A data storage system includes an entry register, a number of storage registers each accommodating data and " vacancy " information, and associated circuits responsive to the vacancy information to control the entry of new information into the registers. Vacancy information is the presence or absence of a character which indicates that no data is to replace the data associated with the character. With each data word also is associated a tag. All the tags are compared in parallel with a tag defined, the required data and the contents of the register holding this tag are read out on the successful comparison being made. As described the vacancy character is a single bit and the circuits comprise cryotron gates. Four types of gate are used differing only in the arrangement of the coils. The gate 2 becomes resistive when a current flows in its single coil; "A" gate 4 is an OR circuit becoming resistive when current is flowing in at least one of the coils; " B " gate 6 is an exclusive-or circuit becoming resistive when current is flowing in only one of the coils; and " C " gate 8 is superconductive if the centre coil and one of the other two coils, or if none of the coils are energized. Figs. 1A to 1D show a storage device including an entry register, two typical word registers and an exit register. The 0, 1 or ON, OFF markings indicate that a unit is storing the bit marked or is in the state marked, if the cryotron gate is superconductive. Read-in.-The data word including vacancy and tag bits is entered into the entry register by applying current to the coil of an appropriate one of the entry pair of each bit store. Thus a vacancy bit of is entered by applying current to the coil 12 which sends gate 14 resistive and permits current to flow through gates 16 and 18 and the coils 20, 24 to send the 0 gates resistive. For read-in the entry-exit bit is 0, and initially the timing signal is off. Under these conditions current flows from source 70, through gate 73, coils 74 and 76, 170 and 172 and similar coils in the order bit stores of the entry register. When the timing signal goes on the contents of the entry register are entered in a word register having a vacancy bit of 0. The value of a vacancy bit is reflected in a set of six cryotron gates-an echo bit set-which control the entry of information into a word register. With the timing signal on current from source 72 flows through gate 104, gate 126 to the lower pair of gates in the echo bit set of the first word register. If the vacancy bit is 1 the current flows through gate 300 and is applied to the echo bit set of the next register. If all registers have a vacancy bit of 1 coil 546 is energized and a no vacancy signal issues on terminal 562. If the vacancy bit is 0 in the first word register (say) current flows through gate 190, coil 192 of A-gate 150, coil 194 of C-gate 196 and coils 210, 212 . . . of entry B-gates of the word register. If, for example, tag bit t is 0, current flows through A gate 201, B-gate 242 and coil 260 which permits current to flow through gate 264 to render gate 394 resistive and energize one of the coils of the 1 C-gate. The new vacancy bit is entered at this time but is not entered in the echo bit set in order that it may not interfere with the entry of its own associated word. In fact, gate C is conductive and current energizes the coils 40 and 38 to result in gate 56 becoming resistive. When the timing signal goes off, current flows through gate 300, gate 302 and coil 304 to enter 1 in the echo bit set. Read-out.-The entry-exit bit is 1 and the required tag is entered in the entry register. It will be assumed that tag bit t is 1 and the tag of the first word register is also 1. With the timing signal off, current from source 72 flows through line 80 and the coils of the entry gates of the exit register while current from source 70 flows through entry register exit control line 78. With the timing signal on, current from source 72 passes through gate 140 to line 142 from where it is applied in parallel to B-gates 567, 569. If the word register tag bit is the same as that in the entry register the B-gate is conductive. Thus if current flows through gate 570 to coil 568 if the required tag bit is 1, and if the word tag bit is 1 current flows in coil 576 to render B-gate 569 conductive. After flowing through gate 292 current is applied to the next tag bit B-gate, and if it passes through all the B-gates is applied to the coils of the exit pair of C-gates, e.g. 272, 274. One of these gates in each bit position becomes conductive and the contents of the word register transferred to the exit register, line 80 no longer being energized. Note that current to line 78 is maintained with timing signal on since current from source 70 then flows through gate 102 and gate 139 to line 78, and that if the required tag bit is 0 and a word tag bit is 0 the B-gate is conductive since neither coil 568 nor coil 596 is energized. Magnetic cores or relays are mentioned as equivalent circuit components.

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