公开(公告)号：JPH11298313A

公开(公告)日：1999-10-29

申请号：JP6066399

申请日：1999-03-08

Applicant: SIEMENS AG ,  IBM

Inventor： HANSON DAVID R ,  MUELLER GERHARD

IPC: H03K19/0175 ,  B24B9/06 ,  B24B37/04 ,  H03K19/00 ,  H03K19/0185 ,  H03K19/094

Abstract: PROBLEM TO BE SOLVED: To process a reduced signal by setting the voltage range of a level shift stage control signal higher than the voltage range of an input signal in accordance with the input signal in a reduced voltage range and setting the voltage range of an output signal lower than the voltage range of the level shift stage control signal. SOLUTION: When a buffer enable signal ENp of a node 312 is allowed, an input signal IN inputted to an input node 314 is sent to nodes 316 and 318 at the entrance of a level shift stage 304 through FETs 308 and 310 having low threshold voltage. The stage 304 operates under the power supply within a complete voltage range VSS to VDD and respectively controls the gates of transistors 320 and 322 constituting an output stage 306 with the range VSS to VDD in accordance with the voltage level of the signal IN. The stage 306 quickly draws an output terminal 334 to either a voltage level VREDUCED from a voltage source 336 or a voltage level VSS.

公开(公告)号：JPH11283365A

公开(公告)日：1999-10-15

申请号：JP35791798

申请日：1998-12-16

Applicant: SIEMENS AG ,  IBM

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  WONG HING

IPC: G11C11/401 ,  G11C7/18 ,  G11C8/14 ,  G11C16/06

Abstract: PROBLEM TO BE SOLVED: To constitute a hierarchical bit line architecture and a word line architecture by providing plural local bit line pairs in respective rows to be connected to memory cells and connecting them to master bit lines. SOLUTION: A bit line architecture 20 has plural local bit lines and plural master bit line pairs in respective rows Cj of a memory array. Respective contacts 29 of via holes are connected to drains or sources of FET switches 27 which are connected to the local bit lines. Switching states of the respective switches 27 are controlled by corresponding control lines 28 prolonging in a column direction. Respective control lines 28 are connected to all switches 27 provided parallel in the column direction. True master bit lines MBLj are selectively connected to true local bit lines LBLj via the switches 27it . On the other hand, the MBLj are selectively connected to complementary local bit lines LBLi via switches 27ic .

公开(公告)号：JP2000312230A

公开(公告)日：2000-11-07

申请号：JP2000075093

申请日：2000-03-17

Applicant: IBM ,  SIEMENS AG

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD ,  HANSON DAVID R

IPC: H03K19/0175 ,  G06F13/28 ,  G11C7/10 ,  G11C11/407 ,  H04L25/02 ,  H04L25/03

Abstract: PROBLEM TO BE SOLVED: To provide a dynamic latch receiver circuit that latches a burst mode data signal in a way of avoiding a low pass filter effect for global pointer transfer. SOLUTION: This circuit 100 includes a series of data latch circuits 138a-138d that are laid out in parallel and attain sequential latch of a data signal sequentially transmitted on a signal data line 14, includes a 1st signal generator that generates 1st pointer signals 122a-122s each of which corresponds to a specific latch circuit and is overlapped temporally with the 1st pointer signal generated precedingly and pulse converters 148 (148a...) and 158 (158a...) that receive the corresponding 1st pointer signal and generates a 2nd pointer signal to be given to the respective latch circuits. Each of the 2nd pointer signals is generated according to a sequence where no overlapping takes place and triggers latching of each data signal.

公开(公告)号：JPH11317507A

公开(公告)日：1999-11-16

申请号：JP36124698

申请日：1998-12-18

Applicant: SIEMENS AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C11/401 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To enable master bit lines to be enhanced in pitch and lessened in line capacitance, by a method wherein the master bit lines are set shorter than a row length, and some of the master bit lines covering memory cells are set larger than local bit lines in pitch. SOLUTION: Master bit lines MBL are interleaved, and the master bit lines MBL are shortened to be half or below as long as a row, whereby the master bit lines MBL can be set wider in pitch than those of conventional technique architecture. All the capacitance of the master bit lines MBL gets smaller with a reduction in the length of the master bit line and with an increase in a space between the adjacent master bit lines. As a space is increased, inter-bit line capacitance between the adjacent master bit lines MBL is decreased, so that all the capacitance of the master bit lines MBL becomes small. When the master bit lines MBL are widened in pitch, DRAMs are improved in yield.

公开(公告)号：JPH11163299A

公开(公告)日：1999-06-18

申请号：JP27395598

申请日：1998-09-28

Applicant: SIEMENS AG ,  IBM

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  HOENIGSCHMID HEINZ

IPC: H01L27/108 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To provide an improved architecture, in which an area penalty is reduced or there is substantially no area penalty in a high-density memory, using a diagonal bit line. SOLUTION: This semiconductor memory has a plurality of diagonal bit lines, having changes in the horizontal direction along a memory cell array 12 for facilitating the access to memory cells and being arranged in a pattern shape and a plurality of dual word lines which are not crossed at right angles with the bit lines, the dual word lines contain a master word line 22 in a first layer and a plurality of local word lines in a second layer, and the local word lines are solved by connection to the master word line 22 in a common line via electrical connections disposed at a plurality of intervals.

公开(公告)号：JPH11163297A

公开(公告)日：1999-06-18

申请号：JP27008198

申请日：1998-09-24

Applicant: SIEMENS AG ,  IBM

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI

IPC: G11C11/403 ,  G11C7/06 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To eliminate remarkable bypass arrangement of a bit line which largely operates on the whole size of a chip, by arranging a master data line switch in a sense amplifier area and occupying spaces at every row corresponding to one driver. SOLUTION: A first part 222a of a driver distributed in a sense amplifier bank is arranged in a stitch area or an idle space formed against a local word line 228. A second part 222b is arranged in a sense amplifier area 224. A master data line switch 220 is provided for an area 226 between segmented parts of a PSET driver or an NSET driver in the sense amplifier area 224. A remarkable bypass arrangement of a bit line which largely operates on the whole size of a chip can be eliminated and space efficiency can be improved.

公开(公告)号：JPH11163296A

公开(公告)日：1999-06-18

申请号：JP27007998

申请日：1998-09-24

Applicant: SIEMENS AG ,  IBM

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI

IPC: G11C11/401 ,  G11C5/02 ,  G11C7/18 ,  G11C11/409 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To reduce number of contact points of a sense amplifier bank, by arranging diffusion area between complementary bit lines, extending diffusion areas in a crossing direction against the direction of a column, and sharing the diffusion areas by means of the other drivers. SOLUTION: A level M0 is provided on an active area AA, complementary bit lines 120 are provided for the level M0 and they are arranged on a first diffusion area 154. Then, a second diffusion area 156 is arranged on the active area AA and the second diffusion area 156 and the first diffusion area 154 are connected and shared by plural NSET drivers 142. A global metal line 152 arranged in M1 is connected to a contact point 146 of the first diffusion area 154 by a connection 168. Thus, the number of the contact points of the sense amplifier bank can be reduced.

公开(公告)号：WO2004112048A3

公开(公告)日：2005-04-07

申请号：PCT/EP2004006019

申请日：2004-06-03

Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  DEBROSSE JOHN ,  HOENIGSCHMID HEINZ ,  LEUSCHNER RAINER ,  MUELLER GERHARD

Inventor： DEBROSSE JOHN ,  HOENIGSCHMID HEINZ ,  LEUSCHNER RAINER ,  MUELLER GERHARD

IPC: G06F11/10 ,  G11C7/24 ,  G11C11/406 ,  G11C29/00 ,  G11C11/15

CPC classification number: G11C7/24 ,  G06F11/106 ,  G11C11/406

Abstract: The present invention relates to a method and apparatus for reducing data errors in a magneto-resistive random access memory (MRAM). According to the disclosed method, data bits and associated error correction code (ECC) check bits are stored into a storage area. Thereafter, the data bits and ECC check bits are read out and any errors are detected and corrected. A data refresh is then initiated based on a count and data bits and associated ECC check bits stored in the storage area are then refreshed by accessing the stored data bits and the associated ECC check bits, and ultimately by checking, correcting and restoring the data bits and the ECC check bits to the storage area.

Abstract translation: 本发明涉及一种用于减少磁阻随机存取存储器（MRAM）中的数据错误的方法和装置。 根据所公开的方法，将数据位和相关联的纠错码（ECC）校验位存储到存储区域中。 此后，读出数据位和ECC校验位，并检测和校正任何错误。 然后基于计数开始数据刷新，然后通过访问存储的数据位和相关联的ECC校验位来刷新存储在存储区域中的相关ECC校验位，并且最终通过检查，校正和恢复数据位 并将ECC校验位存储到存储区域。

公开(公告)号：DE60104979T2

公开(公告)日：2005-08-25

申请号：DE60104979

申请日：2001-01-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： HANSON R ,  MUELLER GERHARD

IPC: H03K19/0175 ,  B24B9/06 ,  B24B37/04 ,  G11C5/06 ,  H03K19/00 ,  H03K19/0185 ,  H03K19/094 ,  G11C7/00

Abstract: A method in an integrated circuit for implementing a reduced voltage repeater circuit on a signal line having thereon reduced voltage signals. The reduced voltage signals has a voltage level that is below VDD. The reduced voltage repeater circuit is configured to be coupled to the signal line and having an input node coupled to a first portion of the signal line for receiving a first reduced voltage signal and an output node coupled to a second portion of the signal line for outputting a second reduced voltage signal. The method includes coupling the input node to the first portion of the signal line. The input node is coupled to an input stage of the reduced voltage repeater circuit. The input stage is configured to receive the first reduced voltage signal on the signal line. The input stage is also coupled to a level shifter stage that is arranged to output a set of level shifter stage control signals responsive to the first reduced voltage signal. A voltage range of the set of level shifter stage control signals is higher than a voltage range associated with the first reduced voltage signal. There is further included coupling the output node to the second portion of the signal line. The output node also is coupled to an output stage of the reduced voltage repeater circuit. The output stage is configured to output the second reduced voltage signal on the output node responsive to the set of level shifter stage control signals. A voltage range of the second reduced voltage signal is lower than the voltage range of the set of level shifter stage control signals.

公开(公告)号：DE60017621D1

公开(公告)日：2005-03-03

申请号：DE60017621

申请日：2000-02-18

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： HANSON DAVID R ,  MUELLER GERHARD

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/41 ,  G11C11/417 ,  H03K19/017 ,  H03K19/0175 ,  H03K17/06