公开(公告)号：WO2004112048A3

公开(公告)日：2005-04-07

申请号：PCT/EP2004006019

申请日：2004-06-03

Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  DEBROSSE JOHN ,  HOENIGSCHMID HEINZ ,  LEUSCHNER RAINER ,  MUELLER GERHARD

Inventor： DEBROSSE JOHN ,  HOENIGSCHMID HEINZ ,  LEUSCHNER RAINER ,  MUELLER GERHARD

IPC: G06F11/10 ,  G11C7/24 ,  G11C11/406 ,  G11C29/00 ,  G11C11/15

CPC classification number: G11C7/24 ,  G06F11/106 ,  G11C11/406

Abstract: The present invention relates to a method and apparatus for reducing data errors in a magneto-resistive random access memory (MRAM). According to the disclosed method, data bits and associated error correction code (ECC) check bits are stored into a storage area. Thereafter, the data bits and ECC check bits are read out and any errors are detected and corrected. A data refresh is then initiated based on a count and data bits and associated ECC check bits stored in the storage area are then refreshed by accessing the stored data bits and the associated ECC check bits, and ultimately by checking, correcting and restoring the data bits and the ECC check bits to the storage area.

Abstract translation: 本发明涉及一种用于减少磁阻随机存取存储器（MRAM）中的数据错误的方法和装置。 根据所公开的方法，将数据位和相关联的纠错码（ECC）校验位存储到存储区域中。 此后，读出数据位和ECC校验位，并检测和校正任何错误。 然后基于计数开始数据刷新，然后通过访问存储的数据位和相关联的ECC校验位来刷新存储在存储区域中的相关ECC校验位，并且最终通过检查，校正和恢复数据位 并将ECC校验位存储到存储区域。

公开(公告)号：JP2002093144A

公开(公告)日：2002-03-29

申请号：JP2001197558

申请日：2001-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  GOGL DIETMAR ,  MUELLER GERHARD ,  LOEER THOMAS

IPC: G11C11/14 ,  G11C7/12 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide a current driver arrangement capable of supplying a large current at a low voltage when the area needs to be small. SOLUTION: In a current driver arrangement described in the above, this problem can be solved by configuring a driver of an n-type field effect transistor and a current source connected in series therewith. Concretely, a current driver arrangement for an MRAM is provided comprising a memory cell field having a plurality of memory cells (Z) at the crossing position of a word line (WL) and a bit line (BL), and drivers (T1, T2) supplied to each end of the above word line (WL) and the above bit line (BL), and allocated to the above word line (WL) and the above bit line (BL).

公开(公告)号：JP2002203390A

公开(公告)日：2002-07-19

申请号：JP2001339916

申请日：2001-11-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  MUELLER GERHARD

IPC: G11C11/14 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/00 ,  G11C8/12 ,  G11C11/15 ,  G11C11/401 ,  G11C11/407

Abstract: PROBLEM TO BE SOLVED: To form a memory in which difference of line length between a com mon data port and column connection points are small and short. SOLUTION: This memory is a data memory having a plurality of banks BK, each bank comprises many memory cells, and matrix state arrangement consisting of rows to which row lines WL are allotted and columns to which column lines BL are allotted is formed. The banks BK are arranged vertically in solid as a stack, ends of the column lines connected to each column driving devices LV, SS are at the edges parallel to the rows of banks, these edges are in a common plane, this plane is extended in the direction of row and is substantially perpendicular to the direction of column. The column driving devices LV, SS of all banks BK are arranged densely in the direction of column, and arranged adjacently to the edge of the stack or near the edge as a block.

公开(公告)号：DE60104979T2

公开(公告)日：2005-08-25

申请号：DE60104979

申请日：2001-01-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： HANSON R ,  MUELLER GERHARD

IPC: H03K19/0175 ,  B24B9/06 ,  B24B37/04 ,  G11C5/06 ,  H03K19/00 ,  H03K19/0185 ,  H03K19/094 ,  G11C7/00

Abstract: A method in an integrated circuit for implementing a reduced voltage repeater circuit on a signal line having thereon reduced voltage signals. The reduced voltage signals has a voltage level that is below VDD. The reduced voltage repeater circuit is configured to be coupled to the signal line and having an input node coupled to a first portion of the signal line for receiving a first reduced voltage signal and an output node coupled to a second portion of the signal line for outputting a second reduced voltage signal. The method includes coupling the input node to the first portion of the signal line. The input node is coupled to an input stage of the reduced voltage repeater circuit. The input stage is configured to receive the first reduced voltage signal on the signal line. The input stage is also coupled to a level shifter stage that is arranged to output a set of level shifter stage control signals responsive to the first reduced voltage signal. A voltage range of the set of level shifter stage control signals is higher than a voltage range associated with the first reduced voltage signal. There is further included coupling the output node to the second portion of the signal line. The output node also is coupled to an output stage of the reduced voltage repeater circuit. The output stage is configured to output the second reduced voltage signal on the output node responsive to the set of level shifter stage control signals. A voltage range of the second reduced voltage signal is lower than the voltage range of the set of level shifter stage control signals.

公开(公告)号：DE60017621D1

公开(公告)日：2005-03-03

申请号：DE60017621

申请日：2000-02-18

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： HANSON DAVID R ,  MUELLER GERHARD

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/41 ,  G11C11/417 ,  H03K19/017 ,  H03K19/0175 ,  H03K17/06

公开(公告)号：DE10315050A1

公开(公告)日：2003-11-27

申请号：DE10315050

申请日：2003-04-02

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD ,  HANSON DAVID

IPC: H03K19/0185 ,  H03L5/00

Abstract: A low voltage level shifter circuit with an embedded latch, implemented on a signal line having thereon low voltage signals. There is included a low voltage level shifter circuit configured to receive a low voltage input signal from a first portion of the signal line and output a higher voltage output signal on a second portion of the signal line. A latching circuit is also included, and is configured to latch the low voltage input signal from the first portion of the signal line.

公开(公告)号：DE10314615A1

公开(公告)日：2003-10-23

申请号：DE10314615

申请日：2003-04-01

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: H03F3/04 ,  H03K19/0175 ,  H03K19/094

Abstract: A repeater circuit having improved switching speed and reduced power consumption is described. The repeater circuit is configured to receive an input signal from a first segment of a signal line and pass the signal to a second segment of the signal line in response to an active control signal.

公开(公告)号：DE10243469A1

公开(公告)日：2003-05-08

申请号：DE10243469

申请日：2002-09-19

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： KIRLHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C29/00 ,  G06F11/16 ,  H01L23/525

Abstract: Multiple conductive paths are provided in a circuit portion between a circuit element and a logic block, enabling repairing of defects in the conductive line coupling the circuit element and logic blocks without the use of fusing.

公开(公告)号：DE60028099T2

公开(公告)日：2006-12-07

申请号：DE60028099

申请日：2000-01-05

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： HANSON DAVID R ,  MUELLER GERHARD

IPC: G11C7/10 ,  G11C11/41 ,  G11C11/409 ,  G11C11/4096 ,  G11C11/417 ,  H03K19/017

Abstract: A high frequency driver circuit is described. The driver produces increased current flow at its output to decrease charging time, thereby enabling higher frequency operations. Increased current flow is achieved by providing an active control signal that increases the magnitude of the overdrive voltage applied to a driver transistor.

公开(公告)号：DE69923097T2

公开(公告)日：2006-03-02

申请号：DE69923097

申请日：1999-03-09

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： HANSON DAVID R ,  MUELLER GERHARD

IPC: H03K19/0175 ,  B24B9/06 ,  B24B37/04 ,  H03K19/00 ,  H03K19/0185 ,  H03K19/094

Abstract: There is disclosed a tri-state buffer circuit for receiving an input signal at a buffer input node and transmitting, responsive to a buffer enable signal, an output signal at a buffer output node. The buffer circuit includes an input stage (202) coupled to the buffer input node (208). The input stage (202) is configured to receive, when the buffer enable signal is enabled, the input signal. The buffer circuit further includes a level shifter stage (204) coupled to the input stage (202). The level shifter stage (204) is arranged to output, when the buffer enable signal is enabled, a set of level shifter stage control signals responsive to the input signal. A voltage range of the set of level shifter stage control signals is higher than a voltage range associated with the input signal. The buffer circuit also includes an output stage (206) coupled to the level shifter stage (204). The output stage (206) is configured to output, when the buffer enable signal is enabled, the output signal (210) on the buffer output node responsive to the set of level shifter stage control signals. The voltage range of the output signal is lower than the voltage range of the set of level shifter stage control signals. The output stage (206) decouples the buffer output node from the input stage and the level shifter stage when the buffer enable signal is disabled.