公开(公告)号：EP3039608A4

公开(公告)日：2017-01-11

申请号：EP13892527

申请日：2013-08-28

Applicant: INTEL CORP

Inventor： DALCHER GREG WILLIAM ,  SAHITA RAVI L ,  SHANMUGAVELAYUTHAM PALANIVELRA ,  YAMADA KOICHI ,  KRISHNASWAMY ARVIND

IPC: G06F21/56 ,  G06F11/30 ,  G06F21/55

CPC classification number: G06F21/566 ,  G06F21/554

Abstract: Technologies for assembling an execution profile of an event are disclosed. The technologies may include monitoring the event for a branch instruction, generating a callback to a security module upon execution of the branch instruction, filtering the callback according to a plurality of event identifiers, and validating a code segment associated with the branch instruction, the code segment including code executed before the branch instruction and code executed after the branch instruction.

Abstract translation: 公开了组装事件的执行简档的技术。 技术可以包括监视分支指令的事件，在执行分支指令时产生对安全模块的回调，根据多个事件标识符过滤回调，以及验证与分支指令相关联的代码段，代码 段包括在分支指令之前执行的代码和在分支指令之后执行的代码。

公开(公告)号：EP2801025A4

公开(公告)日：2015-08-26

申请号：EP12864336

申请日：2012-01-04

Applicant: INTEL CORP

Inventor： THOMAS RAMESH ,  TSENG KUO-LANG ,  SAHITA RAVI L ,  DURHAM DAVID M ,  TALLAM MADHUKAR

IPC: G06F9/30 ,  G06F9/46 ,  G06F12/08 ,  G06F12/14 ,  G06F15/80

CPC classification number: G06F12/145 ,  G06F9/468 ,  G06F12/1425 ,  G06F2009/45583 ,  G06F2009/45587

Abstract: Embodiments of techniques and systems for increasing efficiencies in computing systems using virtual memory are described. In embodiments, instructions which are located in two memory pages in a virtual memory system, such that one of the pages does not permit execution of the instructions located therein, are identified and then executed under temporary permissions that permit execution of the identified instructions. In various embodiments, the temporary permissions may come from modified virtual memory page tables, temporary virtual memory page tables which allow for execution, and/or emulators which have root access. In embodiments, per-core virtual memory page tables may be provided to allow two cores of a computer processor to operate in accordance with different memory access permissions. In embodiments, a physical page permission table may be utilized to provide for maintenance and tracking of per-physical-page memory access permissions. Other embodiments may be described and claimed.

公开(公告)号：EP2761438A4

公开(公告)日：2015-04-22

申请号：EP11873157

申请日：2011-09-30

Applicant: INTEL CORP

Inventor： SMITH NED M ,  SAHITA RAVI L

IPC: G06F9/44 ,  G06F9/06 ,  G06F9/455 ,  G06F21/00 ,  G06F21/44

CPC classification number: G06F21/44 ,  G06F9/45558 ,  G06F21/00 ,  G06F21/575 ,  G06F2009/45562 ,  G06F2009/45566 ,  G06F2009/45587