公开(公告)号：US20200278914A1

公开(公告)日：2020-09-03

申请号：US16647563

申请日：2018-08-27

Applicant: Intel Corporation

Inventor： HISHAM ABU SALAH ,  Arthur Leonard Brown ,  Russell J. Fenger ,  Deepak Samuel Kirubakaran ,  Asit K. Mallick ,  Jacob Jun Pan ,  Srinivas Pandruvada ,  Efraim Rotem ,  Arjan Van De Ven ,  Eliezer Weissmann ,  Rafal J. Wysocki

IPC: G06F11/34 ,  G06F11/30 ,  G06F9/48 ,  G06F9/50

Abstract: In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to: maintain a first utilization metric for a first processing engine; detect a thread transfer from a first processing engine to a second processing engine; and generate, using the first utilization metric for the first processing engine, a second utilization metric for a second processing engine. Other embodiments are described and claimed.

公开(公告)号：US10324862B2

公开(公告)日：2019-06-18

申请号：US15282300

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Rebekah M. Leslie-Hurd ,  Francis X. McKeen ,  Carlos V. Rozas ,  Gilbert Neiger ,  Asit K. Mallick ,  Ittai Anati ,  Ilya Alexandrovich ,  Vedvyas Shanbhogue ,  Somnath Chakrabarti

IPC: G06F3/06 ,  G06F12/12 ,  G06F12/0875 ,  G06F9/455

Abstract: Implementations of the disclosure provide for supporting oversubscription of guest enclave memory pages. In one implementation, a processing device comprising a memory controller unit to access a secure enclave and a processor core, operatively coupled to the memory controller unit. The processing device is to identify a target memory page in memory. The target memory page is associated with a secure enclave of a virtual machine (VM). A data structure comprising context information corresponding to the target memory page is received. A state of the target memory page is determined based on the received data structure. The state indicating whether the target memory page is associated with at least one of: a child memory page or a parent memory page of the VM. Thereupon, an instruction to evict the target memory page from the secure enclave is generated based on the determined state.

公开(公告)号：US10135825B2

公开(公告)日：2018-11-20

申请号：US14582829

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Barry E. Huntley ,  Gilbert Neiger ,  H. Peter Anvin ,  Asit K. Mallick ,  Adriaan Van De Ven ,  Scott D. Rodgers

IPC: G06F21/00 ,  H04L29/06 ,  G06F21/74

Abstract: Embodiments of an invention for protecting supervisor mode information are disclosed. In one embodiment, an apparatus includes a storage location, instruction hardware, execution hardware, and control logic. The storage location is to store an indicator to enable supervisor mode information protection. The instruction hardware is to receive an instruction to access supervisor mode information. The execution hardware is to execute the instruction. The control logic is to prevent execution of the instruction if supervisor mode information protection is enabled and a current privilege level is less privileged than a supervisor mode.

公开(公告)号：US20180007051A1

公开(公告)日：2018-01-04

申请号：US15201447

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Mona Vij ,  Somnath Chakrabarti ,  Carlos V. Rozas ,  Asit K. Mallick

IPC: H04L29/06

CPC classification number: H04L63/10 ,  G06F21/10 ,  G06F21/6245 ,  H04L63/06 ,  H04L63/08

Abstract: A processor of an aspect includes a decode unit to decode an instruction. The instruction to indicate a first structure in a protected container memory and to indicate a second structure in the protected container memory. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to determine whether a status indicator is configured to allow at least one key to be exchanged between the first and second structures, and is to exchange the at least one key between the first and second structures when the status indicator is configured to allow the at least one key to be exchanged between the first and second structures.

公开(公告)号：US20170228233A1

公开(公告)日：2017-08-10

申请号：US15019112

申请日：2016-02-09

Applicant: INTEL CORPORATION

Inventor： Michael Mishaeli ,  Jason W. Brandt ,  Gilbert Neiger ,  Asit K. Mallick ,  Rajesh M. Sankaran ,  Raghunandan Makaram ,  Benjamin C. Chaffin ,  James B. Crossland ,  H. Peter Anvin

IPC: G06F9/30 ,  G06F13/40

CPC classification number: G06F9/3009 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/3851 ,  G06F9/52 ,  G06F13/4068

Abstract: A processor of an aspect includes a decode unit to decode a user-level suspend thread instruction that is to indicate a first alternate state. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the instruction at a user privilege level. The execution unit in response to the instruction, is to: (a) suspend execution of a user-level thread, from which the instruction is to have been received; (b) transition a logical processor, on which the user-level thread was to have been running, to the indicated first alternate state; and (c) resume the execution of the user-level thread, when the logical processor is in the indicated first alternate state, with a latency that is to be less than half a latency that execution of a thread can be resumed when the logical processor is in a halt processor power state.

公开(公告)号：US09069605B2

公开(公告)日：2015-06-30

申请号：US14067223

申请日：2013-10-30

Applicant: Intel Corporation

Inventor： Richard A. Hankins ,  Hong Wang ,  Gautham N. Chinya ,  Trung A. Diep ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Asit K. Mallick ,  Baiju V. Patel ,  James Paul Held ,  Milind B. Girkar ,  Prashant Sethi ,  Xinmin Tian

IPC: G06F9/46 ,  G06F9/48

CPC classification number: G06F9/4843

Abstract: Method, apparatus and system embodiments to schedule OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. A scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.

Abstract translation: 方法，装置和系统实施例来调度不依赖于操作系统的OS无关的“碎片”。 对于至少一个实施例，碎片被调度为由调度器例程而不是操作系统执行。 调度程序例程可以在每个启用的顺控程序上运行。 调度器可以从队列系统检索碎片描述符。 与调度器相关联的定序器然后可以执行由描述符描述的碎片。 还描述和要求保护其他实施例。