公开(公告)号：US11019061B2

公开(公告)日：2021-05-25

申请号：US16194648

申请日：2018-11-19

Applicant: Intel Corporation

Inventor： Barry E. Huntley ,  Gilbert Neiger ,  H. Peter Anvin ,  Asit K. Mallick ,  Adriaan Van De Ven ,  Scott D. Rodgers

IPC: G06F21/00 ,  H04L29/06 ,  G06F21/74

Abstract: Embodiments of an invention for protecting supervisor mode information are disclosed. In one embodiment, an apparatus includes a storage location, instruction hardware, execution hardware, and control logic. The storage location is to store an indicator to enable supervisor mode information protection. The instruction hardware is to receive an instruction to access supervisor mode information. The execution hardware is to execute the instruction. The control logic is to prevent execution of the instruction if supervisor mode information protection is enabled and a current privilege level is less privileged than a supervisor mode.

公开(公告)号：US20190121751A1

公开(公告)日：2019-04-25

申请号：US16134809

申请日：2018-09-18

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Rajesh Sankaran Madukkarumukumana ,  Richard Uhlig ,  Lawrence Smith, III ,  Scott D. Rodgers

IPC: G06F12/14 ,  G06F9/455 ,  G06F12/109

Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

公开(公告)号：US09537738B2

公开(公告)日：2017-01-03

申请号：US14317288

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Brian Delgado ,  Brian S. Payne ,  Barry E. Huntley ,  Scott D. Rodgers

IPC: H04L29/06 ,  H04L12/26 ,  G06F9/455

CPC classification number: H04L43/065 ,  G06F9/45558 ,  G06F2009/45591 ,  H04L63/0807

Abstract: In an embodiment, a processor includes at least one core to execute instructions and a system management monitor to receive a platform query request from an external system, obtain status information regarding a configuration of one or more privileged resources of the processor, and report the status information to the external system. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括执行指令的至少一个核心和用于从外部系统接收平台查询请求的系统管理监视器，获得关于处理器的一个或多个特权资源的配置的状态信息，并且报告状态 信息给外部系统。 描述和要求保护其他实施例。

公开(公告)号：US09405551B2

公开(公告)日：2016-08-02

申请号：US13795720

申请日：2013-03-12

Applicant: Intel Corporation

Inventor： Koichi Yamada ,  Palanivel Rajan Shanmugavelayutham ,  Scott D. Rodgers ,  Barry E. Huntley ,  James D. Beaney, Jr. ,  Boaz Tamir

IPC: G06F15/00 ,  G06F15/76 ,  G06F9/38 ,  G06F9/44 ,  G06F9/455

CPC classification number: G06F9/3885 ,  G06F9/44 ,  G06F9/45516 ,  G06F9/45533 ,  Y02D10/26 ,  Y02D10/28

Abstract: In an embodiment, a processor includes a binary translation (BT) container having code to generate a binary translation of a first code segment and to store the binary translation in a translation cache, a host entity logic to manage the BT container and to identify the first code segment, and protection logic to isolate the BT container from a software stack. In this way, the BT container is configured to be transparent to the software stack. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括具有生成第一代码段的二进制转换和将二进制转换存储在转换高速缓存中的代码的二进制转换（BT）容器，用于管理BT容器的主机实体逻辑，并且识别 第一代码段和用于将BT容器与软件堆栈隔离的保护逻辑。 这样，BT容器被配置为对软件堆栈是透明的。 描述和要求保护其他实施例。

公开(公告)号：US10999284B2

公开(公告)日：2021-05-04

申请号：US17084406

申请日：2020-10-29

Applicant: Intel Corporation

Inventor： Barry E. Huntley ,  Gilbert Neiger ,  H. Peter Anvin ,  Asit K. Mallick ,  Adriaan Van De Ven ,  Scott D. Rodgers

IPC: G06F21/00 ,  H04L29/06 ,  G06F21/74

Abstract: Embodiments of an invention for protecting supervisor mode information are disclosed. In one embodiment, an apparatus includes a storage location, instruction hardware, execution hardware, and control logic. The storage location is to store an indicator to enable supervisor mode information protection. The instruction hardware is to receive an instruction to access supervisor mode information. The execution hardware is to execute the instruction. The control logic is to prevent execution of the instruction if supervisor mode information protection is enabled and a current privilege level is less privileged than a supervisor mode.

公开(公告)号：US10135825B2

公开(公告)日：2018-11-20

申请号：US14582829

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Barry E. Huntley ,  Gilbert Neiger ,  H. Peter Anvin ,  Asit K. Mallick ,  Adriaan Van De Ven ,  Scott D. Rodgers

IPC: G06F21/00 ,  H04L29/06 ,  G06F21/74

Abstract: Embodiments of an invention for protecting supervisor mode information are disclosed. In one embodiment, an apparatus includes a storage location, instruction hardware, execution hardware, and control logic. The storage location is to store an indicator to enable supervisor mode information protection. The instruction hardware is to receive an instruction to access supervisor mode information. The execution hardware is to execute the instruction. The control logic is to prevent execution of the instruction if supervisor mode information protection is enabled and a current privilege level is less privileged than a supervisor mode.

公开(公告)号：US10592421B2

公开(公告)日：2020-03-17

申请号：US15250787

申请日：2016-08-29

Applicant: Intel Corporation

Inventor： Carlos V. Rozas ,  Ilya Alexandrovich ,  Ittai Anati ,  Alex Berenzon ,  Michael A. Goldsmith ,  Barry E. Huntley ,  Anton Ivanov ,  Simon P. Johnson ,  Rebekah M. Leslie-Hurd ,  Francis X. McKeen ,  Gilbert Neiger ,  Rinat Rappoport ,  Scott D. Rodgers ,  Uday R. Savagaonkar ,  Vincent R. Scarlata ,  Vedvyas Shanbhogue ,  Wesley H. Smith ,  William C. Wood

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/00 ,  G06F12/0875 ,  G06F12/0808 ,  G06F12/1027

Abstract: Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.

公开(公告)号：US10114767B2

公开(公告)日：2018-10-30

申请号：US13837822

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Rajesh Sankaran Madukkarumukumana ,  Richard UhligQ ,  Lawrence Smith, III ,  Scott D. Rodgers

IPC: G06F12/10 ,  G06F12/14 ,  G06F9/455 ,  G06F12/109

Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

公开(公告)号：US09164920B2

公开(公告)日：2015-10-20

申请号：US14569069

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Rajesh Sankaran Madukkarumukumana ,  Richard UhligQ ,  Lawrence Smith, III ,  Scott D. Rodgers

IPC: G06F12/10 ,  G06F9/455 ,  G06F12/14

CPC classification number: G06F12/1483 ,  G06F9/45533 ,  G06F9/45558 ,  G06F12/109 ,  G06F2009/45583 ,  G06F2212/151 ,  G06F2212/152 ,  G06F2212/657

Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

Abstract translation: 一种处理器，其包括具有存储器虚拟化支持系统的处理器的虚拟化系统，以将参考映射到由虚拟机上可执行的客户机软件制成的客体物理存储器，该虚拟机器又可在主机上执行，其中处理器可操作为 引用主机的主机物理内存。

公开(公告)号：US09032232B2

公开(公告)日：2015-05-12

申请号：US13786939

申请日：2013-03-06

Applicant: Intel Corporation

Inventor： Martin G. Dixon ,  Scott D. Rodgers ,  Taraneh Bahrami ,  Stephen H. Gunther ,  Prashant Sethi ,  Per Hammarlund

IPC: G06F1/32 ,  G06F12/08 ,  G06F9/30

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3293 ,  G06F9/30083 ,  G06F9/3009 ,  Y02D10/122 ,  Y02D50/20

Abstract: In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.