公开(公告)号：US20220197847A1

公开(公告)日：2022-06-23

申请号：US17674030

申请日：2022-02-17

Applicant: Intel Corporation

Inventor： Stephen R. Van Doren ,  Rajesh M. Sankaran ,  David A. Koufaty ,  Ramacharan Sundararaman ,  Ishwar Agarwal

IPC: G06F13/42 ,  G06F13/14

Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to detect a message to communicate via an interconnect coupled with a device capable of communication via a plurality of interconnect protocols, the plurality of interconnect protocols comprising a non-coherent interconnect protocol, a coherent interconnect protocol, and a memory interconnect protocol. Embodiments also include determining an interconnect protocol of the plurality of interconnect protocols to communicate the message via the interconnect based on the message, and providing the message to a multi-protocol multiplexer coupled with the interconnect, the multi-protocol multiplexer to communicate the message utilizing the interconnect protocol via the interconnect with the device.

公开(公告)号：US11003597B2

公开(公告)日：2021-05-11

申请号：US16229857

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Mingwei Zhang ,  Ravi Sahita ,  David A. Koufaty

IPC: G06F12/14 ,  G06F12/1009 ,  H04L9/08 ,  G06F21/78 ,  G06F12/1027 ,  G06F21/55 ,  G06F21/79 ,  H04L9/00

Abstract: In embodiments, an apparatus for computing includes a protection key register (PKR) having 2N bits, where N is an integer, to store a plurality of permission entries corresponding to protected memory domains, and a protected memory domain controller, coupled to the PKR. In embodiments, the memory domain controller is to: obtain protection key (PK) bits from a page table entry for a target page address; obtain one or more additional PK bits from a target linear memory address; and combine the PK bits and the additional PK bits to form a PK domain number to index into the plurality of permission entries in the PKR to obtain a permission entry for a protected memory domain.

公开(公告)号：US20190205139A1

公开(公告)日：2019-07-04

申请号：US15858899

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Joseph Nuzman ,  Jonas Svennebring ,  Doddaballapur N. Jayasimha ,  Samantika S. Sury ,  David A. Koufaty ,  Niall D. McDonnell ,  Yen-Cheng Liu ,  Stephen R. Van Doren ,  Stephen J. Robinson

IPC: G06F9/30

Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations. In one example, a system includes an RAO instruction queue stored in a memory and having entries grouped by destination cache line, each entry to enqueue an RAO instruction including an opcode, a destination identifier, and source data, optimization circuitry to receive an incoming RAO instruction, scan the RAO instruction queue to detect a matching enqueued RAO instruction identifying a same destination cache line as the incoming RAO instruction, the optimization circuitry further to, responsive to no matching enqueued RAO instruction being detected, enqueue the incoming RAO instruction; and, responsive to a matching enqueued RAO instruction being detected, determine whether the incoming and matching RAO instructions have a same opcode to non-overlapping cache line elements, and, if so, spatially combine the incoming and matching RAO instructions by enqueuing both RAO instructions in a same group of cache line queue entries at different offsets.

公开(公告)号：US10126985B2

公开(公告)日：2018-11-13

申请号：US14748971

申请日：2015-06-24

Applicant: Intel Corporation

Inventor： Subramanya R. Dulloor ,  Rajesh M. Sankaran ,  David A. Koufaty ,  Christopher J. Hughes ,  Jong Soo Park ,  Sheng Li

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0888 ,  G06F9/50 ,  G06F12/08 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/0866

Abstract: A processor includes a processing core to generate a memory request for an application data in an application. The processor also includes a virtual page group memory management (VPGMM) unit coupled to the processing core to specify a caching priority (CP) to the application data for the application. The caching priority identifies importance of the application data in a cache.

公开(公告)号：US10037288B2

公开(公告)日：2018-07-31

申请号：US15088836

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Francesc Bernat Guim ,  David A. Koufaty ,  Andrea Pellegrini ,  Rajesh M. Sankaran

IPC: G06F12/00 ,  G06F12/14 ,  G06F12/1009 ,  G06F21/62 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/1475 ,  G06F12/1009 ,  G06F12/1081 ,  G06F21/6209 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2212/152 ,  G06F2212/656 ,  G06F2212/657

Abstract: A processing system includes a processing core to execute a task and an input output (IO) memory management unit, coupled to the core. The IO memory management unit includes a storage unit to store a page table entry including an identifier of a memory domain and a protection key associated with the identifier. The protection key indicates whether a memory page in the memory domain is accessible. The IO memory management unit also includes a protection key register comprising a field indexed by the protection key, the field including a set of bits reflecting a memory access permission associated with the protection key. The protection key register is, responsive to receiving a request from an IO device to store data associated with the process or the thread of the process, to one of allow or deny permission to access the memory page in the memory domain for storage of the data associated with the process or the thread of the process based on the protection key.

公开(公告)号：US20140189302A1

公开(公告)日：2014-07-03

申请号：US13993547

申请日：2012-12-28

Applicant: INTEL CORPORATION

Inventor： Dheeraj R. Subbareddy ,  Ganapati N. Srinivasa ,  David A. Koufaty ,  Scott D. Hahn ,  Mishali Naik ,  Paolo Narvaez ,  Abirami Prabhakaran ,  Eugene Gorbatov ,  Alon Naveh ,  Inder M. Sodhi ,  Eliezer Weissmann ,  Paul Brett ,  Gaurav Khanna ,  Russell J. Fenger

IPC: G06F9/38

CPC classification number: G06F9/3885 ,  G06F9/5094 ,  Y02D10/22

Abstract: A processor includes multiple physical cores that support multiple logical cores of different core types, where the core types include a big core type and a small core type. A multi-threaded application includes multiple software threads are concurrently executed by a first subset of logical cores in a first time slot. Based on data gathered from monitoring the execution in the first time slot, the processor selects a second subset of logical cores for concurrent execution of the software threads in a second time slot. Each logical core in the second subset has one of the core types that matches the characteristics of one of the software threads.

Abstract translation: 处理器包括多个物理核，其支持不同核心类型的多个逻辑核，其中核心类型包括大型核心类型和小型核心类型。 多线程应用程序包括多个软件线程，由第一时隙中的逻辑核心的第一子集同时执行。 基于从监视第一时隙中的执行收集的数据，处理器在第二时隙中选择用于在软件线程中并发执行的逻辑核心的第二子集。 第二子集中的每个逻辑核心具有与其中一个软件线程的特征相匹配的核心类型之一。

公开(公告)号：US11782866B2

公开(公告)日：2023-10-10

申请号：US17674030

申请日：2022-02-17

Applicant: Intel Corporation

Inventor： Stephen R. Van Doren ,  Rajesh M. Sankaran ,  David A. Koufaty ,  Ramacharan Sundararaman ,  Ishwar Agarwal

IPC: G06F13/42 ,  G06F13/14 ,  G06F13/38

CPC classification number: G06F13/4234 ,  G06F13/14 ,  G06F13/38

Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to detect a message to communicate via an interconnect coupled with a device capable of communication via a plurality of interconnect protocols, the plurality of interconnect protocols comprising a non-coherent interconnect protocol, a coherent interconnect protocol, and a memory interconnect protocol. Embodiments also include determining an interconnect protocol of the plurality of interconnect protocols to communicate the message via the interconnect based on the message, and providing the message to a multi-protocol multiplexer coupled with the interconnect, the multi-protocol multiplexer to communicate the message utilizing the interconnect protocol via the interconnect with the device.

公开(公告)号：US20230112707A1

公开(公告)日：2023-04-13

申请号：US18074232

申请日：2022-12-02

Applicant: Intel Corporation

Inventor： Michael Lemay ,  David A. Koufaty ,  Ravi L. Sahita

IPC: G06F12/14 ,  G06F21/53 ,  G06F21/56

Abstract: Enforcing memory operand types using protection keys is generally described herein. A processor system to provide sandbox execution support for protection key rights attacks includes a processor core to execute a task associated with an untrusted application and execute the task using a designated page of a memory; and a memory management unit to designate the page of the memory to support execution of the untrusted application.

公开(公告)号：US11500636B2

公开(公告)日：2022-11-15

申请号：US16799619

申请日：2020-02-24

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Joseph Nuzman ,  Jonas Svennebring ,  Doddaballapur N. Jayasimha ,  Samantika S. Sury ,  David A. Koufaty ,  Niall D. McDonnell ,  Yen-Cheng Liu ,  Stephen R. Van Doren ,  Stephen J. Robinson

IPC: G06F9/30 ,  G06F12/0875

Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations. In one example, a system includes an RAO instruction queue stored in a memory and having entries grouped by destination cache line, each entry to enqueue an RAO instruction including an opcode, a destination identifier, and source data, optimization circuitry to receive an incoming RAO instruction, scan the RAO instruction queue to detect a matching enqueued RAO instruction identifying a same destination cache line as the incoming RAO instruction, the optimization circuitry further to, responsive to no matching enqueued RAO instruction being detected, enqueue the incoming RAO instruction; and, responsive to a matching enqueued RAO instruction being detected, determine whether the incoming and matching RAO instructions have a same opcode to non-overlapping cache line elements, and, if so, spatially combine the incoming and matching RAO instructions by enqueuing both RAO instructions in a same group of cache line queue entries at different offsets.

公开(公告)号：US20210374087A1

公开(公告)日：2021-12-02

申请号：US17380712

申请日：2021-07-20

Applicant: Intel Corporation

Inventor： David A. Koufaty ,  Rajesh M. Sankaran ,  Utkarsh Y. Kakaiya

IPC: G06F13/42 ,  G06F13/40 ,  G06F9/50 ,  G06F9/54

Abstract: Techniques for increasing link efficiency are disclosed. In one embodiment, a device handle table is created at each end of a link. Device handle allocation messages can be used to associate a particular device handle with a particular domain identifier, such as a bus/device/function (BDF) identifier or a processor address space identifier (PASID). Once a device handle is allocated, messages can be sent between the two ends of the link that include the device handle. The device handle can be used to determine the domain identifier associated with the message. As the device handle can be fewer bits than the domain identifier, the link efficiency can be increased.