公开(公告)号：US20240079337A1

公开(公告)日：2024-03-07

申请号：US17929471

申请日：2022-09-02

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Tchefor Ndukum ,  Kristof Kuwawi Darmawikarta ,  Sheng Li ,  Srinivas V. Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5383 ,  H01L23/49866 ,  H01L23/5381 ,  H01L23/5386 ,  H01L25/0655 ,  H01L24/16

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a conductive pad having a first surface, an opposing second surface, and lateral surfaces extending between the first and second surfaces; a conductive via coupled to the first surface of the conductive pad; a liner on the second surface and on the lateral surfaces of the conductive pad, wherein a material of the liner includes nickel, palladium, or gold; a microelectronic component having a conductive contact; and an interconnect electrically coupling the conductive contact of the microelectronic component and the liner on the second surface of the conductive pad, wherein a material of the interconnect includes nickel or tin.

公开(公告)号：US11894311B2

公开(公告)日：2024-02-06

申请号：US17716955

申请日：2022-04-08

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Islam A. Salama ,  Sri Ranga Sai Boyapati ,  Sheng Li ,  Kristof Darmawikarta ,  Robert L. Sankman ,  Amruthavalli Pallavi Alur

IPC: H01L25/00 ,  H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/25 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/071 ,  H01L25/112 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/22 ,  H01L2224/224 ,  H01L2224/24226 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2924/15311

Abstract: A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

公开(公告)号：US10775873B2

公开(公告)日：2020-09-15

申请号：US16288580

申请日：2019-02-28

Applicant: Intel Corporation

Inventor： Victor W. Lee ,  Edward T. Grochowski ,  Daehyun Kim ,  Yuxin Bai ,  Sheng Li ,  Naveen K. Mellempudi ,  Dhiraj D. Kalamkar

IPC: G06F1/00 ,  G06F1/3287 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3225 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/50

Abstract: In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.

公开(公告)号：US10692965B2

公开(公告)日：2020-06-23

申请号：US16142817

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Chong Zhang ,  Andrew J. Brown ,  Sheng Li ,  Sai Vadlamani ,  Ying Wang

IPC: H01L27/08 ,  H01L49/02 ,  H01F27/28 ,  C09D11/52 ,  H01L23/522 ,  G05F1/625

Abstract: Methods of forming an inductor using dry processes are described. A cavity is laser drilled in an insulator. A first magnetic material layer is printed in the cavity. An Ag conductive ink is printed on the first magnetic material layer and a second magnetic material layer printed on the ink. The ink has a trace sandwiched between the first and second magnetic material layers that provides a majority of the inductance of the inductor. A protective insulating layer protects the second magnetic material layer from a wet chemistry solution when contacts are formed to the ink. The second magnetic material layer and ink are deposited in or on the cavity.

公开(公告)号：US20190341351A1

公开(公告)日：2019-11-07

申请号：US16474026

申请日：2017-03-29

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Islam A. Salama ,  Sri Ranga Sai Boyapati ,  Sheng Li ,  Kristof Darmawikarta ,  Robert L. Sankman ,  Amruthavalli Pallavi Alur

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

公开(公告)号：US10198264B2

公开(公告)日：2019-02-05

申请号：US14969864

申请日：2015-12-15

Applicant: Intel Corporation

Inventor： Asit K. Mishra ,  Deborah T. Marr ,  Jong Soo Park ,  Nadathur Rajagopalan Satish ,  Mikhail Smelyanskiy ,  Michael Anderson ,  Mostofa Ali Patwary ,  Narayanan Sundaram ,  Sheng Li

IPC: G06F9/30

Abstract: A processing device includes a sorting module, which adds to each of a plurality of elements a position value of a corresponding position in a register rest resulting in a plurality of transformed elements in corresponding positions. The plurality of elements include a plurality of bits. The sorting module compares each of the plurality of transformed elements to itself and to one another. The sorting module also assigns one of an enabled or disabled indicator to each of the plurality of the transformed elements based on the comparison. The sorting module further counts a number of the enabled indicators assigned to each of the plurality of the transformed elements to generate a sorted sequence of the plurality of elements.

公开(公告)号：US11196165B2

公开(公告)日：2021-12-07

申请号：US16017093

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Sri Chaitra Chavali ,  Siddharth Alur ,  Sheng Li

IPC: H01Q9/04 ,  H01L23/66 ,  H01Q5/35 ,  H01Q1/22

Abstract: Embodiments include antennas, methods of forming antennas, and a semiconductor package. An antenna includes a feed port disposed in a substrate, and the feed port having a first patch and a second patch. The first patch is disposed on a top surface of substrate, and the second patch is disposed on a bottom surface of substrate. The antenna includes a photoimageable dielectric (PID) disposed on the bottom surface of substrate, where PID surrounds the second patch. The antenna includes a third patch disposed on PID, where the third patch is below the second patch. The antenna includes a cavity disposed between the second and third patches, where the cavity is enclosed by PID and third patch. An additional antenna includes a patch disposed on a first substrate, and a feed port disposed in a second substrate. This antenna includes a composite layer disposed between the first and second substrates.

公开(公告)号：US10672859B2

公开(公告)日：2020-06-02

申请号：US16020590

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Rahul Jain ,  Sheng Li ,  Sai Vadlamani ,  Chong Zhang

IPC: H01L23/522 ,  H01L49/02 ,  H01F17/00 ,  H01L23/00

Abstract: An apparatus and method of forming a magnetic inductor circuit. A substrate is provided and a first magnetic layer is formed in contact with one layer of the substrate. A conductive trace is formed in contact with the first magnetic layer. A sacrificial cooper layer protects the magnetic material from wet chemistry process steps. A conductive connection is formed from the conductive trace to the outside substrate, the conductive connection comprising a horizontal connection formed by in-layer plating. A second magnetic layer is formed in contact with the conductive trace. Instead of a horizontal connection, a vertical conductive connection can be formed that is perpendicular to the magnetic layers, by drilling a first via in a second of the magnetic layers, forming a buildup layer, and drilling a second via through the buildup layer, where the buildup layer protects the magnetic layers from wet chemistry processes.

公开(公告)号：US20190326222A1

公开(公告)日：2019-10-24

申请号：US16473599

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： Sri Chaitra J. Chavali ,  Liwei Cheng ,  Siddharth K. Alur ,  Sheng Li

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L21/027 ,  H01L25/18

Abstract: An apparatus system is provided which comprises: a substrate; a metal pillar formed on the substrate, the metal pillar comprising a first section and a second section, wherein the first section of the metal pillar is formed by depositing metal in a first opening of a first photoresist layer, and wherein the second section of the metal pillar is formed by depositing metal in a second opening of a second photoresist layer.

公开(公告)号：US10126985B2

公开(公告)日：2018-11-13

申请号：US14748971

申请日：2015-06-24

Applicant: Intel Corporation

Inventor： Subramanya R. Dulloor ,  Rajesh M. Sankaran ,  David A. Koufaty ,  Christopher J. Hughes ,  Jong Soo Park ,  Sheng Li

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0888 ,  G06F9/50 ,  G06F12/08 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/0866

Abstract: A processor includes a processing core to generate a memory request for an application data in an application. The processor also includes a virtual page group memory management (VPGMM) unit coupled to the processing core to specify a caching priority (CP) to the application data for the application. The caching priority identifies importance of the application data in a cache.