公开(公告)号：US20200091162A1

公开(公告)日：2020-03-19

申请号：US16132281

申请日：2018-09-14

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L27/11507 ,  H01L27/108 ,  H01L23/522 ,  H01L23/532 ,  G11C11/22

Abstract: Described herein are one access transistor and one ferroelectric capacitor (1T-1FE-CAP) memory cells in diagonal arrangements, as well as corresponding methods and devices. When access transistors of memory cells are implemented as FinFETs, then, in a first diagonal arrangement, memory cells are arranged so that the BLs for the cells are diagonal with respect to the fins of the access transistors of the cells, while the WLs for the cells are perpendicular to the fins. In a second diagonal arrangement, memory cells are arranged so that the fins of the access transistors of the cells are diagonal with respect to the WLs for the cells, while the BLs for the cells are perpendicular to the WLs. Such diagonal arrangements may advantageously allow achieving high layout densities of 1T-1FE-CAP memory cells and may benefit from the re-use of front-end transistor process technology with relatively minor adaptations.

公开(公告)号：US10559349B2

公开(公告)日：2020-02-11

申请号：US16078582

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: G11C11/00 ,  G11C11/412 ,  G11C8/16 ,  G11C11/419 ,  H01L27/11 ,  G11C11/22

Abstract: One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.

公开(公告)号：US20190325932A1

公开(公告)日：2019-10-24

申请号：US16464260

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/04 ,  H01L43/06 ,  H01L43/10 ,  H01L43/14

Abstract: An apparatus is provided which comprises: a first paramagnet; a stack of layers, a portion of which is adjacent to the first paramagnet, wherein the stack of layers is to provide an inverse Rashba-Edelstein effect; a second paramagnet; a magnetoelectric layer adjacent to the second paramagnet; and a conductor coupled to at least a portion of the stack of layers and the magnetoelectric layer.

公开(公告)号：US10331582B2

公开(公告)日：2019-06-25

申请号：US15430765

申请日：2017-02-13

Applicant: INTEL CORPORATION

Inventor： Ishwar S. Bhati ,  Huichu Liu ,  Jayesh Gaur ,  Kunal Korgaonkar ,  Sasikanth Manipatruni ,  Sreenivas Subramoney ,  Tanay Karnik ,  Hong Wang ,  Ian A. Young

IPC: G06F13/16 ,  G06F12/0811

Abstract: A processor includes a processing core and a cache controller including a read queue and a separate write queue. The read queue is to buffer read requests of the processing core to a non-volatile memory, last level cache (NVM-LLC), and the write queue is to buffer write requests to the NVM-LLC. The cache controller is to detect whether the write queue is full. The cache controller further prioritizes a first order of sending requests to the NVM-LLC when the write queue contains an empty slot, the first order specifying a first pattern of sending the read requests before the write requests, and prioritizes a second order of sending requests to the NVM-LLC in response to a determination that the write queue is full, the second order specifying a second pattern of alternating between sending a write request from the write queue and a read request from the read queue.

公开(公告)号：US10236345B2

公开(公告)日：2019-03-19

申请号：US15569269

申请日：2015-06-22

Applicant: Intel Corporation

Inventor： Uygar E. Avci ,  Ian A. Young

IPC: H01L29/267 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/205

Abstract: Fermi filter field effect transistors having a Fermi filter between a source and a source contact, systems incorporating such transistors, and methods for forming them are discussed. Such transistors may include a channel between a source and a drain both having a first polarity and a Fermi filter between the source and a source contact such that the Fermi filter has a second polarity complementary to the first polarity.

公开(公告)号：US20190043549A1

公开(公告)日：2019-02-07

申请号：US16144896

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Kaushik Vaidyanathan ,  Daniel H. Morris ,  Huichu Liu ,  Dileep J. Kurian ,  Uygar E. Avci ,  Tanay Karnik ,  Ian A. Young

IPC: G11C11/22 ,  G11C11/413 ,  G06F1/32

Abstract: Embodiments include apparatuses, methods, and systems associated with save-restore circuitry including metal-ferroelectric-metal (MFM) devices. The save-restore circuitry may be coupled to a bit node and/or bit bar node of a pair of cross-coupled inverters to save the state of the bit node and/or bit bar node when an associated circuit block transitions to a sleep state, and restore the state of the bit node and/or bit bar node when the associated circuit block transitions from the sleep state to an active state. The save-restore circuitry may be used in a flip-flop circuit, a register file circuit, and/or another suitable type of circuit. The save-restore circuitry may include a transmission gate coupled between the bit node (or bit bar node) and an internal node, and an MFM device coupled between the internal node and a plate line. Other embodiments may be described and claimed.

公开(公告)号：US20190036018A1

公开(公告)日：2019-01-31

申请号：US16081001

申请日：2016-03-29

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Ian A. Young ,  Dmitri E. Nikonov ,  Ravi Pillarisetty ,  Uygar E. Avci

IPC: H01L43/10 ,  H01L43/02 ,  H01L43/12 ,  H01F10/32 ,  G11C11/16 ,  G11B5/738

Abstract: Described is an apparatus which comprises: a heat spreading layer; a first transition metal layer adjacent to the heat spreading layer; and a magnetic recording layer adjacent to the first transition metal layer. Described is an apparatus which comprises: a first electrode; a magnetic junction having a free magnet; and one or more layers of Jahn-Teller material adjacent to the first electrode and the free magnet of the magnetic junction.

公开(公告)号：US09947805B2

公开(公告)日：2018-04-17

申请号：US15151381

申请日：2016-05-10

Applicant: Intel Corporation

Inventor： Chytra Pawashe ,  Kevin Lin ,  Anurag Chaudhry ,  Raseong Kim ,  Seiyon Kim ,  Kelin Kuhn ,  Sasikanth Manipatruni ,  Rafael Rios ,  Ian A. Young

IPC: H01H51/22 ,  H01L29/84 ,  H01H59/00 ,  B82Y10/00 ,  H01H1/00 ,  H01L29/04 ,  H01L29/06 ,  H01L29/161 ,  H01H9/02

CPC classification number: H01L29/84 ,  B82Y10/00 ,  H01H1/0094 ,  H01H9/0271 ,  H01H59/0009 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/161

Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.

公开(公告)号：US09711215B2

公开(公告)日：2017-07-18

申请号：US14913676

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: G11C11/16 ,  G11C5/02 ,  G11C5/06 ,  G11C5/08 ,  G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0069 ,  G11C7/12 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/5607 ,  G11C2213/79 ,  G11C2213/82

Abstract: Described is an apparatus comprising: a first select-line; a second select-line; a bit-line; a first bit-cell including a resistive memory element and a transistor, the first bit-cell coupled to the first select-line and the bit-line; a buffer with an input coupled to the first select-line and an output coupled to the second select-line; and a second bit-cell including a resistive memory element and a transistor, the second bit-cell coupled to the second select-line and the bit-line. Described is a magnetic random access memory (MRAM) comprising: a plurality of rows, each row including: a plurality of bit-cells, each bit-cell having an MTJ device coupled to a transistor; and a plurality of buffers, each of which to buffer a select-line signal for a group of bit-cells among the plurality of bit-cells; and a plurality of bit-lines, each row sharing a single bit-line among the plurality of bit-cells in that row.

公开(公告)号：US20170178711A1

公开(公告)日：2017-06-22

申请号：US14975439

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: G11C11/22

CPC classification number: G11C11/223 ,  G11C11/221 ,  G11C11/2297 ,  H03K19/0016 ,  H03K19/18

Abstract: Described is an apparatus which comprises: a first power domain having a first inverter to be powered by a first switchable positive supply and a first switchable negative supply; and a second power domain having a second inverter including p-type and n-type FE-FETs, the second inverter having an input coupled to an output of the first inverter.