公开(公告)号：US20230112575A1

公开(公告)日：2023-04-13

申请号：US18080980

申请日：2022-12-14

Applicant: Intel Corporation

Inventor： Prerna Budhkar ,  Tanvi Sharma ,  Srivatsa Rangachar Srinivasa ,  Dileep John Kurian ,  Tanay Karnik

IPC: G06F12/0864 ,  G06F12/14

Abstract: A hash accelerator of a cache memory may receive a query from a processor comprising the cache memory, the query to comprise an input key and an operation to be performed based on a hash table stored in the cache memory. The hash accelerator may determine whether an entry associated with the input key exists in a lock board of the hash accelerator. The hash accelerator may process the query based on whether the entry exists in the lock board.

公开(公告)号：US20220319162A1

公开(公告)日：2022-10-06

申请号：US17845732

申请日：2022-06-21

Applicant: Intel Corporation

Inventor： Srivatsa Rangachar Srinivasa ,  Tanay Karnik ,  Dileep Kurian ,  Ranganath Krishnan ,  Jainaveen Sundaram Priya ,  Indranil Chakraborty

IPC: G06V10/84 ,  G06F7/544 ,  G06V10/82

Abstract: Methods, apparatus, systems, and articles of manufacture providing a Bayesian compute unit with reconfigurable sampler and methods and apparatus to operate the same are disclosed. An example apparatus includes a number generator to generate a sequence of numbers; a multiplier to generate a plurality of products by multiplying respective numbers of the sequence of the numbers by a variance value; and an adder to generate a plurality of weights by adding a mean value to the plurality of products, the plurality of weights corresponding to a single probability distribution.

公开(公告)号：US10749104B2

公开(公告)日：2020-08-18

申请号：US16217807

申请日：2018-12-12

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Daniel Morris ,  Tanay Karnik ,  Sasikanth Manipatruni ,  Kaushik Vaidyanathan ,  Ian Young

IPC: H01L43/02 ,  H03K19/18 ,  H01L27/22 ,  H01L43/10

Abstract: Some embodiments include apparatuses having a first magnet, a first stack of layers coupled to a first portion of the first magnet, a first layer coupled to a second portion of the first magnet, a second magnet, a second stack of layers coupled to a first portion of the second magnet, a second layer coupled to a second portion of the second magnet, a conductor coupled to the first stack of layers and to the second layer, and a conductive path coupled to the first portion of the first magnet and to the first portion of the second magnet, each of the first and second layers including a magnetoelectric material, each of the first and second stacks of layers providing an inverse spin orbit coupling effect.

公开(公告)号：US10607885B2

公开(公告)日：2020-03-31

申请号：US15085925

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Tanay Karnik ,  William Wahby

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/528

Abstract: Techniques and mechanisms for providing electrical insulation of a through-substrate interconnect (TI). In an embodiment, the TI extends between a first side of the substrate and a second side of the substrate opposite the first side. The substrate has formed therein a conductive shell structure that extends at least partially around a periphery of the TI. A first dielectric liner structure is disposed between the conductive shell structure and a bulk material of the substrate. A second dielectric liner structure is disposed between the conductive shell structure and the TI. In another embodiment, a voltage of the conductive shell structure is allowed to float while the TI exchanges a signal or a supply voltage.

公开(公告)号：US20180285268A1

公开(公告)日：2018-10-04

申请号：US15475197

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Kunal Kishore Korgaonkar ,  Ishwar S. Bhati ,  Huichu Liu ,  Jayesh Gaur ,  Sasikanth Manipatruni ,  Sreenivas Subramoney ,  Tanay Karnik ,  Hong Wang ,  Ian A. Young

IPC: G06F12/0811 ,  G06F12/0808 ,  G06F12/1045 ,  G06F13/40

Abstract: In one embodiment, a processor comprises a processing core, a last level cache (LLC), and a mid-level cache. The mid-level cache is to determine that an idle indicator has been set, wherein the idle indicator is set based on an amount of activity at the LLC, and based on the determination that the idle indicator has been set, identify a first cache line to be evicted from a first set of cache lines of the mid-level cache and send a request to write the first cache line to the LLC.

公开(公告)号：US20180232311A1

公开(公告)日：2018-08-16

申请号：US15430765

申请日：2017-02-13

Applicant: INTEL CORPORATION

Inventor： Ishwar S. Bhati ,  Huichu Liu ,  Jayesh Gaur ,  Kunal Korgaonkar ,  Sasikanth Manipatruni ,  Sreenivas Subramoney ,  Tanay Karnik ,  Hong Wang ,  Ian A. Young

IPC: G06F12/0831 ,  G06F12/0875 ,  G06F12/0811

CPC classification number: G06F13/1642 ,  G06F12/0811

Abstract: A processor includes a processing core and a cache controller including a read queue and a separate write queue. The read queue is to buffer read requests of the processing core to a non-volatile memory, last level cache (NVM-LLC), and the write queue is to buffer write requests to the NVM-LLC. The cache controller is to detect whether the write queue is full. The cache controller further prioritizes a first order of sending requests to the NVM-LLC when the write queue contains an empty slot, the first order specifying a first pattern of sending the read requests before the write requests, and prioritizes a second order of sending requests to the NVM-LLC in response to a determination that the write queue is full, the second order specifying a second pattern of alternating between sending a write request from the write queue and a read request from the read queue.

公开(公告)号：US20160034338A1

公开(公告)日：2016-02-04

申请号：US14878985

申请日：2015-10-08

Applicant: INTEL CORPORATION

Inventor： Keith A. Bowman ,  James W. Tschanz ,  Nam Sung Kim ,  Janice C. Lee ,  Christopher B. Wilkerson ,  Shih-Lien L. Lu ,  Tanay Karnik ,  Vivek K. De

IPC: G06F11/07

CPC classification number: G01R31/3177 ,  G01R31/31723 ,  G01R31/31725 ,  G01R31/31727 ,  G06F1/10 ,  G06F11/0706 ,  G06F11/0757 ,  G06F11/0793 ,  H03K3/0375

Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.

Abstract translation: 提供了具有错误检测的顺序电路。 例如，它们可以用于替代传统的主从触发器，例如在关键路径电路中，以检测并启动在顺序输入处的后期转换的校正。 在一些实施例中，这样的顺序可以包括具有时间借用锁存器的转换检测器。

公开(公告)号：US11411172B2

公开(公告)日：2022-08-09

申请号：US16130912

申请日：2018-09-13

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Sasikanth Manipatruni ,  Daniel Morris ,  Kaushik Vaidyanathan ,  Tanay Karnik ,  Ian Young

IPC: G11C11/00 ,  H01L43/04 ,  H01L43/06 ,  G11C11/16 ,  G11C11/18 ,  H01L43/10

Abstract: An apparatus is provided which comprises a full adder including magnetoelectric material and spin orbit material. In some embodiments, the adder includes: a 3-bit carry generation structure and a multi-bit sum generation structure coupled to the 3-bit carry generation structure. In some embodiments, the 3-bit carry generation structure includes at least three cells comprising magnetoelectric material and spin orbit material, wherein the 3-bit carry generation structure is to perform a minority logic operation on first, second, and third inputs to generate a carry output. In some embodiments, the multi-bit sum generation structure includes at least four cells comprising magnetoelectric material and spin orbit material, wherein the multi-bit sum generation structure is to perform a minority logic operation on the first, second, and third inputs and the carry output to generate a sum output.

公开(公告)号：US11043256B2

公开(公告)日：2021-06-22

申请号：US16458022

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： Kaushik Vaidyanathan ,  Huichu Liu ,  Tanay Karnik ,  Sreenivas Subramoney ,  Jayesh Gaur ,  Sudhanshu Shukla

IPC: G11C11/4096 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4097 ,  G11C11/408 ,  G11C11/4094 ,  G11C7/22

Abstract: Described are mechanisms and methods for amortizing the cost of address decode, row-decode and wordline firing across multiple read accesses (instead of just on one read access). Some or all memory locations that share a wordline (WL) may be read, by walking through column multiplexor addresses (instead of just reading out one column multiplexor address per WL fire or memory access). The mechanisms and methods disclosed herein may advantageously enable N distinct memory words to be read out if the array uses an N-to-1 column multiplexor. Since memories such as embedded DRAMs (eDRAMs) may undergo a destructive read, for a given WL fire, a design may be disposed to sense N distinct memory words and restore them in order.

公开(公告)号：US11037614B2

公开(公告)日：2021-06-15

申请号：US16615780

申请日：2018-07-23

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Sasikanth Manipatruni ,  Ian A. Young ,  Tanay Karnik ,  Daniel H. Morris ,  Kaushik Vaidyanathan

IPC: G11C11/22 ,  H01L27/11507 ,  H01L49/02

Abstract: Described is an apparatus to reduce or eliminate imprint charge, wherein the apparatus which comprises: a source line; a bit-line; a memory bit-cell coupled to the source line and the bit-line; a first multiplexer coupled to the bit-line; a second multiplexer coupled to the source-line; a first driver coupled to the first multiplexer; a second driver coupled to the second multiplexer; and a current source coupled to the first and second drivers.