公开(公告)号：US10516812B2

公开(公告)日：2019-12-24

申请号：US15943617

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Jason Tanner ,  Paul Diefenbaugh ,  Vishal Sinha ,  Arthur Runyan ,  Gary K. Smith ,  Kathy Bui ,  Yifan Li ,  Shirley Huang Meterelliyoz

IPC: G09G5/399 ,  G06T1/60 ,  G09G5/00 ,  H04N5/073 ,  G06F3/14 ,  G09G5/36 ,  G09G5/393

Abstract: Techniques for selective display frame fetching can include receiving or fetching rendered display frames by a display engine. The display engine can determine if a new frame includes one or more dirty portions. If the new frame includes one or more dirty portions, just the dirty portions can be loaded by the display engine into a display buffer. The display engine can also scan out just the dirty portions from the display buffer to a display.

公开(公告)号：US20190222858A1

公开(公告)日：2019-07-18

申请号：US16365546

申请日：2019-03-26

Applicant: Intel Corporation

Inventor： Srinivasan Embar Raghukrishnan ,  Jason Tanner

IPC: H04N19/517 ,  H04N19/105 ,  H04N19/137 ,  H04N19/124 ,  H04N19/96 ,  H04N19/176

CPC classification number: H04N19/517 ,  H04N19/105 ,  H04N19/124 ,  H04N19/137 ,  H04N19/176 ,  H04N19/96

Abstract: Techniques related to coding video using out of loop inter motion estimation are discussed. Such techniques include performing simultaneous motion estimation for multiple blocks using merge candidates such that at least one of the blocks has non-final merge candidates, finalizing the merge candidates for the at least one block, and resolving reference to any non-final merge candidates that became invalid in the finalized merge candidates for final motion estimation.

公开(公告)号：US10225536B2

公开(公告)日：2019-03-05

申请号：US15200420

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Paul S. Diefenbaugh ,  Jason Tanner ,  Kristoffer D. Fleming ,  Vishal R. Sinha ,  Karthik Veeramani

IPC: H04N19/186 ,  G06F17/30 ,  H04N9/64 ,  H04N21/41 ,  H04N21/4363 ,  H04N21/4402

Abstract: Sink devices are provided that increase quality of displayed images by dynamically integrating higher fidelity update frames into a base stream encoded using an encoding technique (e.g., chroma-subsampling and/or another lossless encoding technique). Use of base image frames enables backward compatibility with existing technology and serves as a baseline for bandwidth scaling. The fidelity update frames may include raw image data, lossy, or losslessly compressed image data, and/or additional subsampled image data. The image data included in the fidelity update frames may apply to the entire base image frame or a portion thereof. The fidelity update frames may include incremental data or complete, high fidelity image data for a portion of an entire image. The sink devices may store and implement fidelity management policies that control operation of the devices to balance resource consumption against fidelity to meet the needs of specific operational environments.

公开(公告)号：US10115223B2

公开(公告)日：2018-10-30

申请号：US15476984

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Jason Tanner ,  Paul S. Diefenbaugh ,  Atsuo Kuwahara

IPC: G06T15/00 ,  H04N19/42 ,  H04N19/17 ,  G06T1/60 ,  G06T1/20 ,  G06F1/32 ,  G09G5/36

Abstract: An embodiment of a graphics apparatus may include a frame divider to divide a frame into two or more sub-frames, and a parallelized post-render stage communicatively coupled to the frame divider to process a sub-frame of the two or more sub-frames in parallel with a render operation. The parallelized post-render stage may include a post-processor communicatively coupled to the frame divider to post-process a rendered sub-frame in parallel with the render operation. Other embodiments are disclosed and claimed.

公开(公告)号：US20180309927A1

公开(公告)日：2018-10-25

申请号：US15495525

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Jason Tanner ,  Wen-Fu Kao ,  Ping Liu ,  Yi-Jen Chiu ,  Ya-Ti Peng

IPC: H04N5/232 ,  G06F3/01 ,  H04N21/44 ,  H04N21/442 ,  H04N21/433 ,  H04N21/81 ,  H04N21/414

CPC classification number: H04N5/23238 ,  G06F3/012 ,  H04N21/41407 ,  H04N21/433 ,  H04N21/44008 ,  H04N21/44204 ,  H04N21/44209 ,  H04N21/816

Abstract: Systems, apparatuses and methods may provide for technology to improve an appearance of objects that enter a viewable area of a 360-degree video. The technology may include a head mounted display (HMD), a viewport comprising a viewable area within the HMD, and a memory to store objects of interest not currently in the viewable area.

公开(公告)号：US20170085885A1

公开(公告)日：2017-03-23

申请号：US14857633

申请日：2015-09-17

Applicant: INTEL CORPORATION

Inventor： Jason Tanner

IPC: H04N19/156 ,  H04N19/176 ,  H04N19/105 ,  H04N19/159

CPC classification number: H04N19/156 ,  H04N19/105 ,  H04N19/137 ,  H04N19/146 ,  H04N19/154 ,  H04N19/159 ,  H04N19/176

Abstract: Techniques related to intra coding performance enhancements discussed. Such techniques may include determining intra coding modes based in part on processing performance costs associated with available intra modes and/or generating a block encode order based on intra coding modes, performing encoding, and re-ordering the encoded blocks to a default coding order for bitstream insertion.

公开(公告)号：US20250021381A1

公开(公告)日：2025-01-16

申请号：US18902104

申请日：2024-09-30

Applicant: Intel Corporation

Inventor： Sangeeta Manepalli ,  Chia-Hung S. Kuo ,  Venkateshan Udhayan ,  Stanley Baran ,  Jason Tanner ,  Michael Rosenzweig

IPC: G06F9/48

Abstract: Methods, systems, articles of manufacture and apparatus are disclosed to generate dynamic computing resource schedules. An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to determine a first schedule policy based on (a) an interval parameter and (b) an energy budget parameter, the first schedule policy to include a first instantiation window. The example instructions further determine performance metrics of a target processor circuit based on instantiating a workload with the first schedule policy, and generate a second schedule policy based on the performance metrics of the target processor circuit, the second schedule policy to include a second instantiation window, the second instantiation window including a modification relative to the first instantiation window.

公开(公告)号：US20240107031A1

公开(公告)日：2024-03-28

申请号：US18525001

申请日：2023-11-30

Applicant: Intel Corporation

Inventor： Stanley Baran ,  Jason Tanner ,  Venkateshan Udhayan ,  Chia-Hung S. Kuo

IPC: H04N19/159 ,  G06T7/62 ,  H04N19/167

CPC classification number: H04N19/159 ,  G06T7/62 ,  H04N19/167

Abstract: An example apparatus determines a size of a dirty region of a video frame; after the size of the dirty region satisfies a threshold: encode the dirty region of the video frame to generate an encoded dirty region; and cause storing of the dirty region in the cache; and after the size of the dirty region does not satisfy the threshold: cause storing of the video frame in a volatile memory that is separate from the cache; and encode the video frame via inter-encoding to generate an encoded video frame.

公开(公告)号：US11902570B2

公开(公告)日：2024-02-13

申请号：US16802283

申请日：2020-02-26

Applicant: INTEL CORPORATION

Inventor： Sergei Plotnikov ,  Jason Tanner

IPC: H04N19/567 ,  H04N19/18 ,  H04N19/157 ,  H04N19/176

CPC classification number: H04N19/567 ,  H04N19/157 ,  H04N19/176 ,  H04N19/18

Abstract: Techniques related to reduction of artifacts in parallel block coding mode selection for video are discussed. Such techniques include, for blocks along a parallel processing split boundary of a video frame, coding mode selection that divides a block into sub-blocks, performs motion estimation for the sub-blocks with skip check disabled and using distortion and coefficient coding cost but exclusive of motion vector coding cost, and evaluates a skip check for the block using the sub-block motion vectors.

公开(公告)号：US11284074B2

公开(公告)日：2022-03-22

申请号：US16722497

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Vasily Aristarkhov ,  Jason Tanner

IPC: H04N19/147 ,  H04N19/115 ,  H04N19/14 ,  H04N19/124 ,  H04N19/154 ,  H04N19/172

Abstract: Techniques are provided for multi-channel video encoding with cross-channel look ahead rate control. A methodology implementing the techniques according to an embodiment includes encoding a first video channel to generate a first output bitstream and first channel statistics including a quantization parameter, the first video channel comprising a first plurality of video frames at a first resolution. The method further includes encoding a second video channel to generate a second output bitstream encoded at a bit rate based on the first channel statistics, the second video channel comprising a second plurality of video frames at a second resolution. The second resolution may equal the first resolution depending on target bit rates for the channels. The method further includes performing look ahead processing on the first video channel to generate first channel look ahead statistics, and encoding the second video channel based on the first channel look ahead statistics.