公开(公告)号：US20190288190A1

公开(公告)日：2019-09-19

申请号：US16430201

申请日：2019-06-03

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Christopher J. Wiegand ,  MD Tofizur Rahman ,  Brian S. Doyle ,  Mark L. Doczy ,  Oleg Golonzka ,  Tahir Ghani ,  Justin S. Brockman

IPC: H01L43/12 ,  G11C11/16 ,  H01L43/10 ,  H01F10/32 ,  H01F41/30 ,  H01L43/08

Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such pSTTM devices. In some embodiments, perpendicular MTJ material stacks include a multi-layered filter stack disposed between a fixed magnetic layer and an antiferromagnetic layer or synthetic antiferromagnetic (SAF) stack. In some embodiments, non-magnetic layers of the filter stack include at least one of Ta, Mo, Nb, W, or Hf. These transition metals may be in pure form or alloyed with other constituents.

公开(公告)号：US10418415B2

公开(公告)日：2019-09-17

申请号：US16069165

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Christopher J. Wiegand ,  Oleg Golonzka ,  MD Tofizur Rahman ,  Brian S. Doyle ,  Mark L. Doczy ,  Kevin P. O'Brien ,  Kaan Oguz ,  Tahir Ghani ,  Satyarth Suri

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16 ,  H01F10/32 ,  H01F41/32 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/027 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213

Abstract: Approaches for an interconnect cladding process for integrating magnetic random access memory (MRAM) devices, and the resulting structures, are described. In an example, a memory structure includes an interconnect disposed in a trench of a dielectric layer above a substrate, the interconnect including a diffusion barrier layer disposed at a bottom of and along sidewalls of the trench to an uppermost surface of the dielectric layer, a conductive fill layer disposed on the diffusion barrier layer and recessed below the uppermost surface of the dielectric layer and an uppermost surface of the diffusion barrier layer, and a conductive capping layer disposed on the conductive fill layer and between sidewall portions of the diffusion barrier layer. A memory element is disposed on the conductive capping layer of the interconnect.

公开(公告)号：US20190221734A1

公开(公告)日：2019-07-18

申请号：US16327603

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Brian S. Doyle ,  Mark L. Doczy ,  Charles C. Kuo ,  Daniel G. Ouellette ,  Christopher J. Wiegand ,  MD Tofizur Rahman ,  Brian Maertz

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L43/08 ,  H01L27/228 ,  H01L43/10 ,  H01L43/12

Abstract: Systems, apparatus, and methods for magnetoresitive memory are described. An apparatus for magnetoresitive memory includes a fixed layer, a free layer, and a tunneling barrier between the fixed layer and the free layer. The free layer is a new alloy consisting of a composition of Cobalt (Co), Iron (Fe), and Boron (B) intermixed with a non-magnetic metal according to a ratio. A thin insert layer of CoFeB may optionally be added between the alloy and the tunneling barrier.

公开(公告)号：US20190115353A1

公开(公告)日：2019-04-18

申请号：US16082261

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Brian S. Doyle ,  Kaan Oguz ,  Charles C. Kuo ,  Mark L. Doczy ,  Tejaswi K. Indukuri

IPC: H01L27/1159 ,  H01L27/11587 ,  H01L29/78 ,  G11C11/22

Abstract: A monocrystalline metal-oxide stack including a ferroelectric (FE) tunneling layer and a buffer layer is epitaxially grown on a growth substrate. A first polycrystalline metal electrode layer is deposited over the tunneling layer. A bonding material layer is further deposited over the electrode layer. The bonding material layer is then bonded to a material layer on a front or back side of a host substrate that further comprises a transistor cell. Once bonded, the growth substrate may be removed from the metal-oxide stack to complete a transfer of the metal-oxide stack from the growth substrate to the host substrate. A second polycrystalline metal electrode layer is then deposited over the exposed buffer layer, placing both electrodes in close proximity to the FE tunneling layer.

公开(公告)号：US20180248114A1

公开(公告)日：2018-08-30

申请号：US15755444

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Christopher J. Wiegand ,  MD Tofizur Rahman ,  Brian S. Doyle ,  Mark L. Doczy ,  Oleg Golonzka ,  Tahir Ghani ,  Justin S. Brockman

IPC: H01L43/08 ,  H01L43/02 ,  H01F10/32 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16 ,  H01L43/12 ,  H01F41/30

Abstract: MTJ material stacks, pSTTM devices employing such stacks, and computing platforms employing such STTM devices. In some embodiments, perpendicular MTJ material stacks with free magnetic layers are magnetically coupled through a metal material layer for improved stability and low damping. In some advantageous embodiments, layers of a free magnetic material stack are magnetically coupled through a coupling layer of a metal comprising at least molybdenum (Mo). The Mo may be in pure form or alloyed with other constituents.

公开(公告)号：US10008557B2

公开(公告)日：2018-06-26

申请号：US15342872

申请日：2016-11-03

Applicant: Intel Corporation

Inventor： Christopher J. Jezewski ,  Kevin P. O'Brien

IPC: H01L21/00 ,  H01L23/00 ,  H01L49/02 ,  H01L23/48 ,  H01L21/768 ,  H01L23/64 ,  H01L21/48 ,  H01L23/522

CPC classification number: H01L28/10 ,  H01L21/4814 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.

公开(公告)号：US20250113599A1

公开(公告)日：2025-04-03

申请号：US18477414

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Rachel A. Steinhardt ,  Kevin P. O'Brien ,  Ashish Verma Penumatcha ,  Carl Hugo Naylor ,  Kirby Maxey ,  Pratyush P. Buragohain ,  Chelsey Dorow ,  Mahmut Sami Kavrik ,  Wouter Mortelmans ,  Marko Radosavljevic ,  Uygar E. Avci ,  Matthew V. Metz

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/26 ,  H01L29/66 ,  H01L29/775

Abstract: Methods for doping 2D transistor devices and resulting architectures. The use and placement of oxide dopants, such as, but not limited to, GeOx, enable control over threshold voltage performance and contact resistance of 2D transistor devices. Architectures include distinct stoichiometry compositions.

公开(公告)号：US20240429301A1

公开(公告)日：2024-12-26

申请号：US18341467

申请日：2023-06-26

Applicant: Intel Corporation

Inventor： Rachel A. Steinhardt ,  Dmitri Evgenievich Nikonov ,  Kevin P. O'Brien ,  John J. Plombon ,  Tristan A. Tronic ,  Ian Alexander Young ,  Matthew V. Metz ,  Marko Radosavljevic ,  Carly Rogan ,  Brandon Holybee ,  Raseong Kim ,  Punyashloka Debashis ,  Dominique A. Adams ,  I-Cheng Tung ,  Arnab Sen Gupta ,  Gauri Auluck ,  Scott B. Clendenning ,  Pratyush P. Buragohain

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: A transistor device may be formed with a doped perovskite material as a channel region. The doped perovskite material may be formed via an epitaxial growth process from a seed layer, and the channel regions of the transistor device may be formed from lateral overgrowth from the epitaxial growth process.

公开(公告)号：US20240355934A1

公开(公告)日：2024-10-24

申请号：US18304659

申请日：2023-04-21

Applicant: Intel Corporation

Inventor： Mahmut Sami Kavrik ,  Tristan A. Tronic ,  Jennifer Lux ,  Uygar E. Avci ,  Kevin P. O'Brien

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/66969 ,  H01L29/0847 ,  H01L29/24

Abstract: Described herein are transistors with monolayer transition metal dichalcogenides (TMD) semiconductor material. TMD materials include combination of a transition metal (e.g., molybdenum or tungsten) and a chalcogen (e.g., sulfur or selenium) in a monolayer having a hexagonal crystal structure. A transistor has a single layer of TMD forming a channel region, and multiple layers of the TMD material at the source and drain regions. Upper portions of the multilayer TMD source and drain regions are doped, and conductive contacts are formed over the doped portions.

公开(公告)号：US12107060B2

公开(公告)日：2024-10-01

申请号：US17025843

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Zhiguo Qian ,  Gerald S. Pasdast ,  Mohammad Enamul Kabir ,  Han Wui Then ,  Kimin Jun ,  Kevin P. O'Brien ,  Johanna M. Swan ,  Shawna M. Liff ,  Aleksandar Aleksov ,  Feras Eid

IPC: H01L23/00 ,  H01L25/065 ,  H01L49/02

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0657 ,  H01L28/10 ,  H01L2224/05147 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0801 ,  H01L2224/08145 ,  H01L2224/0903 ,  H01L2224/09055 ,  H01L2224/29186 ,  H01L2224/32145

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.