公开(公告)号：US12278289B2

公开(公告)日：2025-04-15

申请号：US18414290

申请日：2024-01-16

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Carl Naylor ,  Chelsey Dorow ,  Kirby Maxey ,  Tanay Gosavi ,  Ashish Verma Penumatcha ,  Shriram Shivaraman ,  Chia-Ching Lin ,  Sudarat Lee ,  Uygar E. Avci

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.

公开(公告)号：US20250113521A1

公开(公告)日：2025-04-03

申请号：US18478626

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Andrey Vyatskikh ,  Paul B. Fischer ,  Paul Killian Nordeen ,  Uygar E. Avci ,  Mahmut Sami Kavrik ,  Ande Kitamura ,  Kirby Maxey ,  Carl Hugo Naylor ,  Kevin P. O'Brien

IPC: H01L29/775 ,  H01L21/762

Abstract: A transition metal dichalcogenide (TMD) monolayer grown on a growth substrate is directly transferred to a target substrate. Eliminating the use of a carrier wafer in the TMD monolayer transfer process reduces the number of transfers endured by the TMD monolayer from two to one, which can result in less damage to the TMD monolayer. After a TMD monolayer is grown on a growth layer, a protective layer is formed on the TMD monolayer. The protective layer is bonded to the target substrate by a diffusion bonding layer. The direct transfer of TMD monolayers can be repeated to create a stack of TMD monolayers. A stack of TMD monolayers can be used in a field effect transistor, such as a nanoribbon field effect transistor.

公开(公告)号：US20250006841A1

公开(公告)日：2025-01-02

申请号：US18345127

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Dmitri Evgenievich Nikonov ,  John J. Plombon ,  Rachel A. Steinhardt ,  Punyashloka Debashis ,  Kevin P. O'Brien ,  Matthew V. Metz ,  Scott B. Clendenning ,  Brandon Holybee ,  Marko Radosavljevic ,  Ian Alexander Young ,  I-Cheng Tung ,  Sudarat Lee ,  Raseong Kim ,  Pratyush P. Buragohain

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/221 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a transistor includes a gate of strontium ruthenate and a ferroelectric gate dielectric layer of barium titanate. In order to prevent migration of ruthenium from the strontium ruthenate to the barium titanate, a barrier layer is placed between the gate and the ferroelectric gate dielectric layer. The barrier layer may be a metal oxide, such as strontium oxide, barium oxide, zirconium oxide, etc.

公开(公告)号：US20250006839A1

公开(公告)日：2025-01-02

申请号：US18343203

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Dmitri Evgenievich Nikonov ,  Rachel A. Steinhardt ,  Pratyush P. Buragohain ,  John J. Plombon ,  Hai Li ,  Gauri Auluck ,  I-Cheng Tung ,  Tristan A. Tronic ,  Dominique A. Adams ,  Punyashloka Debashis ,  Raseong Kim ,  Carly Rogan ,  Arnab Sen Gupta ,  Brandon Holybee ,  Marko Radosavljevic ,  Uygar E. Avci ,  Ian Alexander Young ,  Matthew V. Metz

IPC: H01L29/78 ,  H01L29/24 ,  H01L29/49 ,  H01L29/66

Abstract: A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first p-type perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second p-type perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and the gate materials.

公开(公告)号：US20240186416A1

公开(公告)日：2024-06-06

申请号：US18414290

申请日：2024-01-16

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Carl NAYLOR ,  Chelsey DOROW ,  Kirby MAXEY ,  Tanay GOSAVI ,  Ashish Verma PENUMATCHA ,  Shriram SHIVARAMAN ,  Chia-Ching LIN ,  Sudarat LEE ,  Uygar E. AVCI

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/6681 ,  H01L21/02568 ,  H01L21/0262

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.

公开(公告)号：US20220199546A1

公开(公告)日：2022-06-23

申请号：US17127382

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Gerald S. Pasdast ,  Kimin Jun ,  Zhiguo Qian ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Shawna M. Liff ,  Mohammad Enamul Kabir ,  Feras Eid ,  Kevin P. O'Brien ,  Han Wui Then

IPC: H01L23/552 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/66

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component, having a first surface and an opposing second surface including a first direct bonding region at the second surface with first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component, having a first surface and an opposing second surface, including a second direct bonding region at the first surface with second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the second microelectronic component is coupled to the first microelectronic component by the first and second direct bonding regions; and a shield structure in the first direct bonding dielectric material at least partially surrounding the one or more of the first metal contacts.

公开(公告)号：US20220093547A1

公开(公告)日：2022-03-24

申请号：US17025843

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Zhiguo Qian ,  Gerald S. Pasdast ,  Mohammad Enamul Kabir ,  Han Wui Then ,  Kimin Jun ,  Kevin P. O'Brien ,  Johanna M. Swan ,  Shawna M. Liff ,  Aleksandar Aleksov ,  Feras Eid

IPC: H01L23/00 ,  H01L25/065 ,  H01L49/02

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

公开(公告)号：US11189790B2

公开(公告)日：2021-11-30

申请号：US16320789

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Sarah E. Atanasov ,  Kevin P. O'Brien ,  Robert L. Bristol

IPC: H01L45/00 ,  H01L27/24

Abstract: Spacer-based patterning for tight-pitch and low-variability random access memory (RAM) bit cells, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate having a top layer. An array of non-volatile random access memory (RAM) bit cells is disposed on the top layer of the substrate. The array of non-volatile RAM bit cells includes columns of non-volatile RAM bit cells along a first direction and rows of non-volatile RAM bit cells along a second direction orthogonal to the first direction. A plurality of recesses is in the top layer of the substrate, along the first direction between columns of the array of non-volatile RAM bit cells.

公开(公告)号：US20200051724A1

公开(公告)日：2020-02-13

申请号：US15735622

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Kaan Oguz ,  Kevin P. O'Brien ,  David L. Kencke ,  Charles C. Kuo ,  Mark L. Doczy ,  Satyarth Suri ,  Robert S. Chau

IPC: H01F10/193 ,  H01F10/32 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: An embodiment includes an apparatus comprising: a substrate; a magnetic tunnel junction (MTJ), on the substrate, comprising a fixed layer, a free layer, and a dielectric layer between the fixed and free layers; and a first synthetic anti-ferromagnetic (SAF) layer, a second SAF layer, and an intermediate layer, which includes a non-magnetic metal, between the first and second SAF layers; wherein the first SAF layer includes a Heusler alloy. Other embodiments are described herein.

公开(公告)号：US10559744B2

公开(公告)日：2020-02-11

申请号：US16072301

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Brian Maertz ,  Christopher J. Wiegand ,  Daniel G. Oeullette ,  Md Tofizur Rahman ,  Oleg Golonzka ,  Justin S. Brockman ,  Tahir Ghani ,  Brian S. Doyle ,  Kevin P. O'Brien ,  Mark L. Doczy ,  Kaan Oguz

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

Abstract: An apparatus including an array of memory cells arranged in a grid defined by word lines and bit lines in a generally orthogonal orientation relative to one another, a memory cell including a resistive memory component and an access transistor, wherein the access transistor includes a diffusion region disposed at an acute angle relative to an associated word line. A method including etching a substrate to form a plurality of fins each including a body having a length dimension including a plurality of first junction regions and a plurality of second junction regions that are generally parallel to one another and offset by angled channel regions displacing in the length dimension an end of a first junction region from the beginning of a second junction region; removing the spacer material; and introducing a gate electrode on the channel region of each of the plurality of fins.