公开(公告)号：US11054884B2

公开(公告)日：2021-07-06

申请号：US15375756

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Brian J. Skerry ,  Ira Weiny ,  Patrick Connor ,  Tsung-Yuan C. Tai ,  Alexander W. Min

IPC: G06F1/3234 ,  G06F1/3209 ,  H04L12/931

Abstract: A computer-implemented method can include receiving a queue depth for a receive queue of a network interface controller (NIC), determining whether a power state of a central processing unit (CPU) core mapped to the receive queue should be adjusted based on the queue depth, and adjusting the power state of the CPU core responsive to a determination that the power state of the CPU core should be adjusted.

公开(公告)号：US10860374B2

公开(公告)日：2020-12-08

申请号：US14866869

申请日：2015-09-26

Applicant: Intel Corporation

Inventor： James Robert Hearn ,  Patrick Connor ,  Kapil Sood ,  Scott P. Dubai ,  Andrew J. Herdrich

IPC: G06F3/00 ,  G06F9/50 ,  G06F9/4401 ,  G06F9/48 ,  G06F13/362

Abstract: In one embodiment, a system comprises platform logic comprising a plurality of processor cores and resource allocation logic. The resource allocation logic may receive a processing request and direct the processing request to a processor core of the plurality of processor cores, wherein the processor core is selected based at least in part on telemetry data associated with the platform logic, the telemetry data indicating a topology of at least a portion of the platform logic.

公开(公告)号：US20200244577A1

公开(公告)日：2020-07-30

申请号：US16850708

申请日：2020-04-16

Applicant: Intel Corporation

Inventor： Iosif Gasparakis ,  Peter P. Waskiewicz, JR. ,  Patrick Connor

IPC: H04L12/741 ,  H04L29/08 ,  H04L29/06 ,  H04L12/863 ,  H04L29/12

Abstract: Methods, apparatus, and systems for implementing in Network Interface Controller (NIC) flow switching. Switching operations are effected via hardware-based forwarding mechanisms in apparatus such as NICs in a manner that does not employ use of computer system processor resources and is transparent to operating systems hosted by such computer systems. The forwarding mechanisms are configured to move or copy Media Access Control (MAC) frame data between receive (Rx) and transmit (Tx) queues associated with different NIC ports that may be on the same NIC or separate NICs. The hardware-based switching operations effect forwarding of MAC frames between NIC ports using memory operations, thus reducing external network traffic, internal interconnect traffic, and processor workload associated with packet processing.

公开(公告)号：US10091063B2

公开(公告)日：2018-10-02

申请号：US14583658

申请日：2014-12-27

Applicant: INTEL CORPORATION

Inventor： Alexander W. Min ,  Ira Weiny ,  Patrick Connor ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai ,  Brian J. Skerry, Jr. ,  Iosif Gasparakis ,  Steven R. Carbonari ,  Daniel J. Dahle ,  Thomas M. Slaight ,  Nrupal R. Jani

IPC: G06F15/173 ,  H04L12/24 ,  H04L12/911

Abstract: Technologies to monitor and manage platform, device, processor and power characteristics throughout a system utilizing a remote entity such as controller node. By remotely monitoring and managing system operation and performance over time, future system performance requirements may be anticipated, allowing system parameters to be adjusted proactively in a more coordinated way. The controller node may monitor, control and predict traffic flows in the system and provide performance modification instructions to any of the computer nodes and a network switch to better optimize performance. The target systems collaborate with the controller node by respectively monitoring internal resources, such as resource availability and performance requirements to provide necessary resources for optimizing operating parameters of the system. The controller node may collect local system information for one or all of the computer nodes to dynamically steer traffic to a specific set of computers for processing to meet desired performance and power requirements.

公开(公告)号：US20180181421A1

公开(公告)日：2018-06-28

申请号：US15391777

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Patrick Connor ,  Scott P. Dubal ,  James R. Hearn ,  Iosif Gasparakis ,  Chris Pavlas ,  Eliezer Tamir

IPC: G06F9/455 ,  G06F9/50

CPC classification number: G06F9/45558 ,  G06F9/54 ,  G06F15/17306 ,  G06F2009/45583

Abstract: An example computer system for transferring a packet includes a hypervisor to run a first virtual machine and a second virtual machine. The computer system also includes a first memory address space associated with the first virtual machine to store the packet. The computer system further includes a second memory address space associated with the second virtual machine to receive and store the packet. The computer system also includes a virtual switch coupled to the first virtual machine and the second virtual machine to detect that the packet is to be sent from the first virtual machine to the second virtual machine. The computer system further includes a direct memory access device to copy the packet from the first memory address space to the second memory address space via the direct memory access device.

公开(公告)号：US20250139040A1

公开(公告)日：2025-05-01

申请号：US18988607

申请日：2024-12-19

Applicant: Intel Corporation

Inventor： Anjali Singhai Jain ,  Naren Mididaddi ,  Arunkumar Balakrishnan ,  Tamar Bar-Kanarik ,  Ji Li ,  Cristian Florin Dumitrescu ,  Shweta Shrivastava ,  Patrick Connor

IPC: G06F13/40 ,  G06F13/16

Abstract: An apparatus includes a host interface; a network interface; hardware storage to store a flow table; and programmable circuitry comprising processors to implement network interface functionality and to: implement a hash table and an age context table, wherein the hash table and the age context table are to reference flow rules maintained in the flow table; process a synchronization packet for a flow by adding a flow rule for the flow to the flow table, adding a hash entry corresponding to the flow rule to the hash table, and adding an age context entry for the flow to the age context table; and process subsequent packets for the flow by performing a first lookup at the hash table to access the flow rule at the flow table and by performing a second lookup at the age context table to apply aging rules to the flow rule in the flow table.

公开(公告)号：US20210405730A1

公开(公告)日：2021-12-30

申请号：US17364523

申请日：2021-06-30

Applicant: Intel Corporation

Inventor： Brian J. Skerry ,  Ira Weiny ,  Patrick Connor ,  Tsung-Yuan C. Tai ,  Alexander W. Min

IPC: G06F1/3234 ,  G06F1/3209

Abstract: A computer-implemented method can include receiving a queue depth for a receive queue of a network interface controller (NIC), determining whether a power state of a central processing unit (CPU) core mapped to the receive queue should be adjusted based on the queue depth, and adjusting the power state of the CPU core responsive to a determination that the power state of the CPU core should be adjusted.

公开(公告)号：US11036531B2

公开(公告)日：2021-06-15

申请号：US15635124

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Patrick Connor ,  James R. Hearn ,  Scott P. Dubal ,  Andrew J. Herdrich ,  Kapil Sood

IPC: G06F9/455

Abstract: Examples may include techniques to live migrate a virtual machine (VM) using disaggregated computing resources including compute and memory resources. Examples include copying data between allocated memory resources that serve as near or far memory for compute resources supporting the VM at a source or destination server in order to initiate and complete the live migration of the VM.

公开(公告)号：US20200280324A1

公开(公告)日：2020-09-03

申请号：US16815666

申请日：2020-03-11

Applicant: Intel Corporation

Inventor： Patrick Connor ,  Kapil Sood ,  Scott Dubal ,  Andrew Herdrich ,  James Hearn

IPC: H03M13/09 ,  H03M13/29 ,  H03M13/25 ,  H03M13/37 ,  H04L1/00

Abstract: Technologies for applying a redundancy encoding scheme to segmented portions of a data block include an endpoint computing device communicatively coupled to a destination computing device. The endpoint computing device is configured to divide a block of data into a plurality of data segments as a function of a transmit window size and a redundancy encoding scheme, and generate redundant data usable to reconstruct each of the plurality of data segments. The endpoint computing device is additionally configured to format a series of network packets that each includes a data segment of the plurality of data segments and generated redundant data for at least one other data segment of the plurality of data segments. Further, the endpoint computing device is configured to transport each of the series of network packets to a destination computing device. Other embodiments are described herein.

公开(公告)号：US10684973B2

公开(公告)日：2020-06-16

申请号：US14014775

申请日：2013-08-30

Applicant: Intel Corporation

Inventor： Patrick Connor ,  Matthew A. Jared ,  Duke C. Hong ,  Elizabeth M. Kappler ,  Chris Pavlas ,  Scott P. Dubal

IPC: G06F13/28 ,  G06F13/40

Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address. The many-to-many and many-to-one peripheral switches forwards the transaction packets internally within the switch based on the destination address such that the packets are forwarded to a node via which the memory address can be accessed. The platform architectures may also be configured to support migration operations in response to failure or replacement of a node.