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公开(公告)号:US11520700B2
公开(公告)日:2022-12-06
申请号:US17042037
申请日:2018-06-29
Applicant: Intel Corporation
Inventor: Malini K. Bhandaru , Iosif Gasparakis , Sunku Ranganath , Liyong Qiao , Rui Zang , Dakshina Ilangovan , Shaohe Feng , Edwin Verplanke , Priya Autee , Lin A. Yang
IPC: G06F12/08 , G06F9/50 , G06F9/54 , G06F12/0806
Abstract: A holistic view of cache class of service (CLOS) to include an allocation of processor cache resources to a plurality of CLOS. The allocation of processor cache resources to include allocation of cache ways for an n-way set of associative cache. Examples include monitoring usage of the plurality of CLOS to determine processor cache resource usage and to report the processor cache resource usage.
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公开(公告)号:US11388053B2
公开(公告)日:2022-07-12
申请号:US16687271
申请日:2019-11-18
Applicant: Intel Corporation
Inventor: Iosif Gasparakis , Ronen Chayat , John Fastabend
IPC: H04L12/24 , H04L41/082 , H04L67/00 , H04L67/04
Abstract: Technologies for controlling operation of a compute node coupled to a computer network via a computing device that includes communications for communicating with the computer network and persistent instructions such as firmware for providing control functions to the computing device, wherein the control functions being defined at least in part by protocol data. An update control module of the computing device may receive update data from a remote node in the computer network via the communications, wherein the update data comprising new protocol data for the persistent instructions. A protocol parser module may parse the update data and generate metadata relating to the update data. A classifier module may receive rules for the control functions, wherein the rules are based at least in part on the update data and metadata. A compiler may compile the parsed update data to the persistent instructions for providing new control functions to the computing device based at least in part on the received rules.
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公开(公告)号:US20200244577A1
公开(公告)日:2020-07-30
申请号:US16850708
申请日:2020-04-16
Applicant: Intel Corporation
Inventor: Iosif Gasparakis , Peter P. Waskiewicz, JR. , Patrick Connor
IPC: H04L12/741 , H04L29/08 , H04L29/06 , H04L12/863 , H04L29/12
Abstract: Methods, apparatus, and systems for implementing in Network Interface Controller (NIC) flow switching. Switching operations are effected via hardware-based forwarding mechanisms in apparatus such as NICs in a manner that does not employ use of computer system processor resources and is transparent to operating systems hosted by such computer systems. The forwarding mechanisms are configured to move or copy Media Access Control (MAC) frame data between receive (Rx) and transmit (Tx) queues associated with different NIC ports that may be on the same NIC or separate NICs. The hardware-based switching operations effect forwarding of MAC frames between NIC ports using memory operations, thus reducing external network traffic, internal interconnect traffic, and processor workload associated with packet processing.
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公开(公告)号:US10091063B2
公开(公告)日:2018-10-02
申请号:US14583658
申请日:2014-12-27
Applicant: INTEL CORPORATION
Inventor: Alexander W. Min , Ira Weiny , Patrick Connor , Jr-Shian Tsai , Tsung-Yuan C. Tai , Brian J. Skerry, Jr. , Iosif Gasparakis , Steven R. Carbonari , Daniel J. Dahle , Thomas M. Slaight , Nrupal R. Jani
IPC: G06F15/173 , H04L12/24 , H04L12/911
Abstract: Technologies to monitor and manage platform, device, processor and power characteristics throughout a system utilizing a remote entity such as controller node. By remotely monitoring and managing system operation and performance over time, future system performance requirements may be anticipated, allowing system parameters to be adjusted proactively in a more coordinated way. The controller node may monitor, control and predict traffic flows in the system and provide performance modification instructions to any of the computer nodes and a network switch to better optimize performance. The target systems collaborate with the controller node by respectively monitoring internal resources, such as resource availability and performance requirements to provide necessary resources for optimizing operating parameters of the system. The controller node may collect local system information for one or all of the computer nodes to dynamically steer traffic to a specific set of computers for processing to meet desired performance and power requirements.
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公开(公告)号:US20180181421A1
公开(公告)日:2018-06-28
申请号:US15391777
申请日:2016-12-27
Applicant: Intel Corporation
Inventor: Patrick Connor , Scott P. Dubal , James R. Hearn , Iosif Gasparakis , Chris Pavlas , Eliezer Tamir
CPC classification number: G06F9/45558 , G06F9/54 , G06F15/17306 , G06F2009/45583
Abstract: An example computer system for transferring a packet includes a hypervisor to run a first virtual machine and a second virtual machine. The computer system also includes a first memory address space associated with the first virtual machine to store the packet. The computer system further includes a second memory address space associated with the second virtual machine to receive and store the packet. The computer system also includes a virtual switch coupled to the first virtual machine and the second virtual machine to detect that the packet is to be sent from the first virtual machine to the second virtual machine. The computer system further includes a direct memory access device to copy the packet from the first memory address space to the second memory address space via the direct memory access device.
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公开(公告)号:US10666727B2
公开(公告)日:2020-05-26
申请号:US15465254
申请日:2017-03-21
Applicant: Intel Corporation
Inventor: Praveen Mala , Iosif Gasparakis
IPC: H04L29/08
Abstract: Generally discussed herein are systems, devices, and methods for data distribution in a distributed data processing system (DDPS). A device of a distributed data processing system may include a storage device to store data regarding data nodes (DNs), switches, and racks on which the DNs and at least some of the switches reside, and circuitry to receive, from a name node or a client node of the DDPS and coupled to the device, a first communication indicating one or more DNs to which a portion of a file is to be replicated, determine a component in a data path between the client node and one or more of the DNs at which to mirror the portion of the file, and provide a second communication indicating the component at which the data is to be mirrored, one or more of the DNs to receive the portion of the tile, and the corresponding one or more of the racks on which the DNs reside.
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公开(公告)号:US20200021486A1
公开(公告)日:2020-01-16
申请号:US16582798
申请日:2019-09-25
Applicant: Intel Corporation
Inventor: Iosif Gasparakis , Ronen Chayat , John Fastabend
Abstract: Technologies for controlling operation of a compute node coupled to a computer network via a computing device that includes communications for communicating with the computer network and persistent instructions such as firmware for providing control functions to the computing device, wherein the control functions being defined at least in part by protocol data. An update control module of the computing device may receive update data from a remote node in the computer network via the communications, wherein the update data comprising new protocol data for the persistent instructions. A protocol parser module may parse the update data and generate metadata relating to the update data. A classifier module may receive rules for the control functions, wherein the rules are based at least in part on the update data and metadata. A compiler may compile the parsed update data to the persistent instructions for providing new control functions to the computing device based at least in part on the received rules.
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公开(公告)号:US20190158412A1
公开(公告)日:2019-05-23
申请号:US16258852
申请日:2019-01-28
Applicant: Intel Corporation
Inventor: Iosif Gasparakis , Brian P. Johnson , Patrick G. Kutch
IPC: H04L12/801 , H04L29/08 , H04L12/24 , G06F9/48
CPC classification number: H04L47/33 , G06F9/48 , H04L41/044 , H04L47/35 , H04L67/1002 , H04L67/327 , H04L69/321 , H04L69/329
Abstract: Technologies for aligning network flows to processing resources include a computing device having multiple processing nodes, a network switch, and a network controller operating in a software-defined network. Each processing node of the computing device may include a processor, memory, and network adapter. The network switch may receive a network packet and request forwarding information from the network controller. The network controller may determine flow information corresponding to the network packet that indicates the application targeted by the network packet and the processing node executing the application. The flow information may be transmitted to the computing device, which may program a flow filter in the network adapter of the processing node executing the application. The network controller may also transmit forwarding information to the network switch, which may forward the received network packet to the network adapter of the processing node executing the application based on the forwarding information.
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公开(公告)号:US20190044828A1
公开(公告)日:2019-02-07
申请号:US16140938
申请日:2018-09-25
Applicant: Intel Corporation
Inventor: Iosif Gasparakis , Malini Bhandaru , Ranganath Sunku
IPC: H04L12/24 , G06F12/084 , G06F9/455 , H04L29/08 , H04L12/26 , H04L12/911
Abstract: Technologies for managing cache quality of service (QoS) include a compute node that includes a network interface controller (NIC) configured to identify a total amount of available shared cache ways of a last level cache (LLC) of the compute node and identify a destination address for each of a plurality of virtual machines (VMs) managed by the compute node. The NIC is further configured to calculate a recommended amount of cache ways for each workload type associated with VMs based on network traffic to be received by the NIC and processed by each of the VMs, wherein the recommended amount of cache ways includes a recommended amount of hardware I/O LLC cache ways and a recommended amount of isolated LLC cache ways usable to update a cache QoS register that includes the recommended amount of cache ways for each workload type. Other embodiments are described herein.
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公开(公告)号:US09910692B2
公开(公告)日:2018-03-06
申请号:US15006320
申请日:2016-01-26
Applicant: Intel Corporation
Inventor: Stephen T. Palermo , Scott P. Dubal , Trevor Cooper , Anjali S. Jain , Iosif Gasparakis , Jr-Shian Tsai , Mike Bursell , Pradeepsunder Ganesh , Parthasarathy Sangam , Jesse C. Brandeburg
CPC classification number: G06F9/45558 , G06F9/5011 , G06F2009/45583 , G06F2009/45595
Abstract: The present disclosure is directed to enhanced virtual function capabilities in a virtualized network environment. In general, devices may comprise physical and virtualized resources. The physical resources may comprise at least a network adaptor that may handle incoming data from a network and outgoing data to the network. The virtualized resources may comprise at least one virtual machine (VM) and a corresponding interface. The corresponding interface may be one of a physical interface, a virtual interface or a “super” virtual interface. The physical interface may provide a first set of capabilities allowing the VM to access (e.g., control) at least the network adaptor. The virtual interface may provide a second set of capabilities that is a subset of the first set. The super virtual interface may provide a third set of capabilities including the second set of capabilities and at least one additional capability from the first set of capabilities.
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