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    Pillar select transistor for 3-dimensional cross point memory
    25.
    发明授权
    Pillar select transistor for 3-dimensional cross point memory 有权

    公开(公告)号：US12268011B2

    公开(公告)日：2025-04-01

    申请号：US17118385

    申请日：2020-12-10

    Applicant: Intel Corporation

    Inventor： Prashant Majhi ,  Derchang Kau ,  Max Hineman

    IPC: H01L27/00 ,  G11C5/06 ,  G11C13/00 ,  H01L27/06 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

    Abstract: A memory device structure includes a vertical transistor having a channel between a source and a drain, a gate electrode adjacent the channel, where the gate electrode is in a first direction orthogonal to a longitudinal axis of the channel. A gate dielectric layer is between the gate electrode and the channel A first terminal of a first interconnect is coupled with the source or the drain, where the first interconnect is colinear with the longitudinal axis. The memory device structure further includes a pair of memory cells, where individual ones of the memory cells includes a selector and a memory element, where a first terminal of the individual ones of the memory cell is coupled to a respective second and a third terminal of the first interconnect. A second terminal of the individual ones of the memory cell is coupled to individual ones of the pair of second interconnects.

    Double-gated ferroelectric field-effect transistor
    26.
    发明授权
    Double-gated ferroelectric field-effect transistor 有权

    公开(公告)号：US11895846B2

    公开(公告)日：2024-02-06

    申请号：US17673670

    申请日：2022-02-16

    Applicant: Intel Corporation

    Inventor： Abhishek A. Sharma ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Prashant Majhi ,  Elijah V. Karpov

    IPC: H01L21/00 ,  H10B51/30 ,  G11C11/22 ,  H01L29/51 ,  H01L29/78

    CPC classification number: H10B51/30 ,  G11C11/223 ,  H01L29/516 ,  H01L29/7831 ,  G11C11/2257 ,  G11C11/2273

    Abstract: A ferroelectric field-effect transistor (FeFET) includes first and second gate electrodes, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, a first gate dielectric between the semiconductor region and the first gate electrode, and a second gate dielectric between the semiconductor region and the second gate electrode. The first gate dielectric includes a ferroelectric dielectric. In an embodiment, a memory cell includes this FeFET, with the first gate electrode being electrically connected to a wordline and the drain region being electrically connected to a bitline. In another embodiment, a memory array includes wordlines extending in a first direction, bitlines extending in a second direction, and a plurality of such memory cells at crossing regions of the wordlines and the bitlines. In each memory cell, the wordline is a corresponding one of the wordlines and the bitline is a corresponding one of the bitlines.

    REPLACEMENT VIA AND BURIED OR BACKSIDE POWER RAIL
    27.
    发明公开
    REPLACEMENT VIA AND BURIED OR BACKSIDE POWER RAIL 审中-公开

    公开(公告)号：US20230197613A1

    公开(公告)日：2023-06-22

    申请号：US17556414

    申请日：2021-12-20

    Applicant: Intel Corporation

    Inventor： Prashant Majhi ,  Klaus Max Schruefer ,  Anand Murthy

    IPC: H01L23/528 ,  H01L23/532 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L21/768

    CPC classification number: H01L23/5286 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/42392 ,  H01L29/0665 ,  H01L29/78696 ,  H01L21/76877

    Abstract: An integrated circuit structure includes a first sub-fin, a second sub-fin laterally spaced from the first sub-fin, a first transistor device over the first sub-fin and having a first contact, a second transistor device over the second sub-fin and having a second contact, and a continuous and monolithic body of conductive material extending vertically between the first and second transistor devices and the first and second sub-fins. The body of conductive material has (i) an upper portion between the first and second transistor devices and (ii) a lower portion between the first and second sub-fins. A continuous conformal layer extends along a sidewall of the lower portion of the body and a sidewall of the upper portion of the body. The integrated circuit structure further comprises a conductive interconnect feature connecting the upper portion of the body to at least one of the first and second contacts.

    STAIRCASE-BASED METAL-INSULATOR-METAL (MIM) CAPACITORS
    28.
    发明公开
    STAIRCASE-BASED METAL-INSULATOR-METAL (MIM) CAPACITORS 审中-公开

    公开(公告)号：US20230163063A1

    公开(公告)日：2023-05-25

    申请号：US17455698

    申请日：2021-11-19

    Applicant: Intel Corporation

    Inventor： Prashant Majhi ,  Anand Murthy

    IPC: H01L23/522 ,  H01L49/02

    CPC classification number: H01L23/5223 ,  H01L28/60

    Abstract: Multi-plate MIM capacitors include a staircase structure, with steps including a high-k capacitor dielectric and one or more electrode plates. Contacts pass through insulator fill material and land on the electrode plate of a respective step. A recess passes through the staircase structure. In some examples, the recess is filled with insulator material, and steps of the staircase structure have a bilayer structure (e.g., lower layer of capacitor dielectric and upper layer of capacitor electrode plate). In other examples, the recess is filled with conductive material. In such cases, steps of the staircase structure have a multilayer structure that includes an upper portion and a lower portion. The lower portion includes insulator material and the upper portion includes a layer of capacitor dielectric between first and second capacitor electrode plates, with the second capacitor electrode plates being continuous with, or otherwise in contact with, the conductive material in the recess.

    IC including back-end-of-line (BEOL) transistors with crystalline channel material
    30.
    发明授权
    IC including back-end-of-line (BEOL) transistors with crystalline channel material 有权

    公开(公告)号：US11616057B2

    公开(公告)日：2023-03-28

    申请号：US16367144

    申请日：2019-03-27

    Applicant: Intel Corporation

    Inventor： Prashant Majhi ,  Abhishek Sharma ,  Brian Doyle ,  Ravi Pillarisetty ,  Willy Rachmady

    IPC: H01L27/06 ,  H01L23/528 ,  H01L21/02 ,  H01L29/267

    Abstract: IC device including back-end-of-line (BEOL) transistors with crystalline channel material. A BEOL crystalline seed may be formed over a dielectric layer that has been planarized over a front-end-of-line (FEOL) transistor level that employs a monocrystalline substrate semiconductor. The BEOL crystalline seed may be epitaxial to the substrate semiconductor, or may have crystallinity independent of that of the substrate semiconductor. The BEOL crystalline seed may comprise a first material having a higher melt temperature than a melt material formed over the seed and over the dielectric layer. Through rapid melt growth, the melt material may be heated to a temperature sufficient to transition from an as-deposited state to a more crystalline state that is derived from, and therefore associated with, the BEOL crystalline seed. A BEOL transistor may then be fabricated from the crystallized material.

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