公开(公告)号：US20160155682A1

公开(公告)日：2016-06-02

申请号：US15019931

申请日：2016-02-09

Applicant: INTEL CORPORATION

Inventor： Sandeep Ahuja ,  Eric W. Buddrius ,  Roger D. Flynn ,  Rajat Agarwal

IPC: H01L23/36 ,  H01L25/00 ,  H01L25/065 ,  H01L23/433 ,  H01L21/48

CPC classification number: H01L23/36 ,  G06F1/20 ,  H01L21/4882 ,  H01L23/433 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H05K7/20445 ,  Y10T29/49002 ,  H01L2924/00

Abstract: In at least some embodiments, an electronic package to maximize heat transfer comprises a plurality of components on a substrate. A stiffener plate is installed over the components. The stiffener plate has openings to expose the components. A plurality of individual integrated heat spreaders are installed within the openings over the components. A first thermal interface material layer (TIM1) is deposited between the components and the plurality of individual integrated heat spreaders. In at least some embodiments, the thickness of the TIM1 is minimized for the components.

Abstract translation: 在至少一些实施例中，使热传递最大化的电子封装包括在基板上的多个部件。 组件上安装有加强板。 加强板具有露出部件的开口。 多个单独的集成散热器安装在部件的开口内。 第一热界面材料层（TIM1）沉积在组件和多个单独的集成散热器之间。 在至少一些实施例中，对于部件，TIM1的厚度最小化。

公开(公告)号：US20250094275A1

公开(公告)日：2025-03-20

申请号：US18808871

申请日：2024-08-19

Applicant: Intel Corporation

Inventor： Sergej Deutsch ,  David M. Durham ,  Karanvir Grewal ,  Rajat Agarwal

IPC: G06F11/10 ,  G06F3/06

Abstract: The technology disclosed herein comprises a processor; a memory to store data and a plurality of error correcting code (ECC) bits associated with the data; and a memory controller coupled to the memory, the memory controller to receive a write request from the processor and, when an access control field is selected in the write request, perform an exclusive OR (XOR) operation on the plurality of ECC bits and a fixed encoding pattern to generate a plurality of encoded ECC bits and store the data and the plurality of encoded ECC bits in the memory.

公开(公告)号：US12235720B2

公开(公告)日：2025-02-25

申请号：US18268956

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Rajat Agarwal ,  Hsing-Min Chen ,  Wei P. Chen ,  Wei Wu ,  Jing Ling ,  Kuljit S. Bains ,  Kjersten E. Criss ,  Deep K. Buch ,  Theodros Yigzaw ,  John G. Holm ,  Andrew M. Rudoff ,  Vaibhav Singh ,  Sreenivas Mandava

IPC: G06F11/10

Abstract: A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

公开(公告)号：US20240053904A1

公开(公告)日：2024-02-15

申请号：US17944352

申请日：2022-09-14

Applicant: Intel Corporation

Inventor： Sergej Deutsch ,  David M. Durham ,  Karanvir Grewal ,  Rajat Agarwal

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0673 ,  G06F3/0629

Abstract: The technology disclosed herein comprises a processor; a memory to store data and a plurality of error correcting code (ECC) bits associated with the data; and a memory controller coupled to the memory, the memory controller to receive a write request from the processor and, when an access control field is selected in the write request, perform an exclusive OR (XOR) operation on the plurality of ECC bits and a fixed encoding pattern to generate a plurality of encoded ECC bits and store the data and the plurality of encoded ECC bits in the memory.

公开(公告)号：US11036634B2

公开(公告)日：2021-06-15

申请号：US16258486

申请日：2019-01-25

Applicant: INTEL CORPORATION

Inventor： Wei Chen ,  Rajat Agarwal ,  Jing Ling ,  Daniel W. Liu

IPC: G06F12/0808 ,  G06F12/0866 ,  G06F1/3287 ,  G06F3/06 ,  G06F12/06 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/128 ,  G06F12/12

Abstract: Provided are an apparatus, system, and method to flush modified data from a first memory to a persistent second memory. A first memory controller coupled to the first memory includes at least one RAS controller to read a range of addresses in the first memory. In response to receiving a command from the power control unit, the at least one RAS controller is invoked to read data from at least one range of addresses specified for the RAS controller from the first memory. A second memory controller transfers data read from the first memory determined to be modified to the second memory. The first memory controller sends a signal to the power control unit to indicate that the modified data in the range of addresses specified for the RAS controller was flushed to the second memory in response to the RAS controller completing reading the range of addresses.

公开(公告)号：US10997082B2

公开(公告)日：2021-05-04

申请号：US16451086

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Andy Rudoff ,  Tiffany J. Kasanicky ,  Wei P. Chen ,  Rajat Agarwal ,  Chet R. Douglas

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/02

Abstract: According to various aspects, a memory system may include: a memory having a memory address space associated therewith to access the memory; a cache memory assigned to the memory; one or more processors configured to generate a dummy address space in addition to the memory address space, each address of the dummy address space being distinct from any address of the memory address space, and generate one or more invalid cache entries in the cache memory, the one or more invalid cache entries referencing one or more dummy addresses of the dummy address space.

公开(公告)号：US10963404B2

公开(公告)日：2021-03-30

申请号：US16017430

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： James A. McCall ,  Rajat Agarwal ,  George Vergis ,  Bill Nale

IPC: G06F13/28 ,  G06F13/16

Abstract: A DIMM is described. The DIMM includes circuitry to simultaneously transfer data of different ranks of memory chips on the DIMM over a same data bus during a same burst write sequence.

公开(公告)号：US10884958B2

公开(公告)日：2021-01-05

申请号：US16017515

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Rajat Agarwal ,  Bill Nale ,  Chong J. Zhao ,  James A. McCall ,  George Vergis

IPC: G06F13/16 ,  G06F13/28

Abstract: A DIMM is described. The DIMM includes circuitry to multiplex write data to different groups of memory chips on the DIMM during a same burst write sequence.

公开(公告)号：US10579464B2

公开(公告)日：2020-03-03

申请号：US15912450

申请日：2018-03-05

Applicant: INTEL CORPORATION

Inventor： Debaleena Das ,  Rajat Agarwal ,  Brian S. Morris

IPC: G06F11/07 ,  G06F3/06 ,  G06F11/10

Abstract: Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having write data for locations in one of the cache lines, the write data for a location in the cache line having an error is written to an entry in a sparing directory including an address of the cache line.

公开(公告)号：US10459809B2

公开(公告)日：2019-10-29

申请号：US15640182

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Hussein Alameer ,  Uksong Kang ,  Kjersten E. Criss ,  Rajat Agarwal ,  Wei Wu ,  John B. Halbert

IPC: G11C5/02 ,  G06F11/16 ,  G06F11/10 ,  G11C5/04 ,  G11C7/10 ,  G11C29/42 ,  G11C29/52 ,  G11C29/00 ,  G11C7/24 ,  H01L25/065 ,  G11C29/04

Abstract: A stacked memory chip device is described. The stacked memory chip device includes a plurality of stacked memory chips. The stacked memory chip device includes read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips. The stacked memory chip device includes data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive information of a particular one of the cache lines is not stored in a same memory chip with the respective substantive information.