公开(公告)号：US20190043552A1

公开(公告)日：2019-02-07

申请号：US16106911

申请日：2018-08-21

Applicant: Intel Corporation

Inventor： Hussein Alameer ,  Kjersten Criss ,  Uksong Kang

IPC: G11C11/4076 ,  H01L27/02

CPC classification number: G11C11/4076 ,  G06F12/08 ,  G11C5/04 ,  G11C5/066 ,  G11C11/4093 ,  G11C2207/105 ,  H01L27/0207

Abstract: An embodiment of a semiconductor apparatus may include technology to provide two or more dynamic random access memory devices, and provide access to the two or more dynamic random access memory devices with two or more pseudo-channels per memory channel. Other embodiments are disclosed and claimed.

公开(公告)号：US10770129B2

公开(公告)日：2020-09-08

申请号：US16106911

申请日：2018-08-21

Applicant: Intel Corporation

Inventor： Hussein Alameer ,  Kjersten Criss ,  Uksong Kang

IPC: G11C5/06 ,  G11C11/4076 ,  H01L27/02 ,  G11C5/04 ,  G06F12/08 ,  G11C11/4093

Abstract: An embodiment of a semiconductor apparatus may include technology to provide two or more dynamic random access memory devices, and provide access to the two or more dynamic random access memory devices with two or more pseudo-channels per memory channel. Other embodiments are disclosed and claimed.

公开(公告)号：US10755753B2

公开(公告)日：2020-08-25

申请号：US16277797

申请日：2019-02-15

Applicant: Intel Corporation

Inventor： Uksong Kang ,  Christopher E. Cox

IPC: G11C7/10 ,  G11C11/406 ,  G11C11/408 ,  G11C7/22 ,  H04L29/06 ,  G11C16/10 ,  G11C11/4093 ,  G11C11/4096 ,  G06K9/00

Abstract: A memory subsystem is enabled with a write pattern command. The write pattern command can have a different command encoding from other write commands. The write pattern command triggers a dynamic random access memory (DRAM) device to write a data pattern that is internally generated, instead of a bit pattern on the data signal lines of the data bus. The internally generated data pattern can be read from a register, such as a mode register. In response to a write pattern command, the DRAM device provides the write pattern data from the register to the memory array to write. Thus, the memory controller does not need to send the data to the memory device.

公开(公告)号：US10599206B2

公开(公告)日：2020-03-24

申请号：US15939101

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Uksong Kang

IPC: G06F1/00 ,  G06F1/324 ,  G06F3/06 ,  G06F1/3234 ,  G11C7/10 ,  G11C11/4072 ,  G06F1/3296 ,  G11C11/4078 ,  G11C11/4076

Abstract: Examples include techniques to change a mode of operation for a memory device. Examples include using information stored at a memory array of the memory device to program mode registers at the memory device to change the mode of operation to a first mode of operation that corresponds to a frequency set point associated with dynamic voltage and frequency scaling for a processor coupled with the memory device.

公开(公告)号：US10482947B2

公开(公告)日：2019-11-19

申请号：US15911068

申请日：2018-03-02

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Uksong Kang ,  Nagi Aboulenein

IPC: G06F3/06 ,  G06F11/10 ,  G11C11/408 ,  G11C29/52

Abstract: A multi-die memory device having fixed bandwidth interfaces can selectively connect portions of the interfaces of the multiple memory dies as a memory channel for the multi-die device. The selective application of the interface bits of the memory dies enables the application of ECC (error checking and correction) in memory devices that otherwise have insufficient connectors to exchange ECC information. The device includes circuitry to selectively apply CAS (column address select) signals to the memory dies to selectively connect the connectors of the memory dies. CAS selection can provide various configurations in which selected bits of a first memory die interface are combined with selected bit or bits of a second memory die interface to provide the device interface. The memory dies can operate in byte mode to apply only half of their data I/O (input/output) interface, with CAS doubled up to provide access to the memory arrays.

公开(公告)号：US10459809B2

公开(公告)日：2019-10-29

申请号：US15640182

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Hussein Alameer ,  Uksong Kang ,  Kjersten E. Criss ,  Rajat Agarwal ,  Wei Wu ,  John B. Halbert

IPC: G11C5/02 ,  G06F11/16 ,  G06F11/10 ,  G11C5/04 ,  G11C7/10 ,  G11C29/42 ,  G11C29/52 ,  G11C29/00 ,  G11C7/24 ,  H01L25/065 ,  G11C29/04

Abstract: A stacked memory chip device is described. The stacked memory chip device includes a plurality of stacked memory chips. The stacked memory chip device includes read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips. The stacked memory chip device includes data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive information of a particular one of the cache lines is not stored in a same memory chip with the respective substantive information.

公开(公告)号：US11010304B2

公开(公告)日：2021-05-18

申请号：US15865642

申请日：2018-01-09

Applicant: Intel Corporation

Inventor： Uksong Kang ,  Kjersten E. Criss ,  Rajat Agarwal ,  John B. Halbert

IPC: G11C29/00 ,  H04L1/00 ,  G06F12/0879 ,  G06F3/06 ,  G06F12/02 ,  G11C11/16 ,  G11C11/408 ,  G06F11/10 ,  G06F12/0846 ,  G11C7/10 ,  G06F12/0893 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/409 ,  G11C29/42 ,  G06F12/06

Abstract: A method performed by a memory is described. The method includes sensing first bits from a first activated column associated with a first sub-word line structure simultaneously with the sensing of second bits from a second activated column associated with a second sub-word line structure. The method also includes providing the first bits at a same first bit location within different read words of a burst read sequence and providing the second bits at a same second bit location within the different read words of the burst read sequence.

公开(公告)号：US10249351B2

公开(公告)日：2019-04-02

申请号：US15804920

申请日：2017-11-06

Applicant: Intel Corporation

Inventor： Uksong Kang ,  Christopher E. Cox

IPC: G11C16/10 ,  G11C7/10 ,  G11C11/406 ,  G11C11/408 ,  G11C7/22 ,  H04L29/06 ,  G11C11/4093 ,  G11C11/4096 ,  G06K9/00

Abstract: A memory subsystem is enabled with a write pattern command. The write pattern command can have a different command encoding from other write commands. The write pattern command triggers a dynamic random access memory (DRAM) device to write a data pattern that is internally generated, instead of a bit pattern on the data signal lines of the data bus. The internally generated data pattern can be read from a register, such as a mode register. In response to a write pattern command, the DRAM device provides the write pattern data from the register to the memory array to write. Thus, the memory controller does not need to send the data to the memory device.

公开(公告)号：US20180137005A1

公开(公告)日：2018-05-17

申请号：US15814336

申请日：2017-11-15

Applicant: Intel Corporation

Inventor： Wei Wu ,  Uksong Kang ,  Hussein Alameer ,  Rajat Agarwal ,  Kjersten E. Criss ,  John B. Halbert

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/108 ,  G11C5/063 ,  G11C7/10 ,  G11C11/40618 ,  G11C11/4093 ,  G11C29/44 ,  G11C29/52 ,  G11C29/835 ,  G11C29/846

Abstract: In a memory system a multichip memory provides data redundancy for error recovery. The multichip memory can be an integrated circuit package with multiple memory dies or memory devices integrated with a common package. The multiple memory dies are coupled in a daisy chain, and can be a vertical stack or in a planar formation. The memory chip or chips at the end of the chain store parity data, and the other devices store data. The multichip memory includes XOR (exclusive OR) logic to compute parity to store in the redundant parity chips.