公开(公告)号：US20230238444A1

公开(公告)日：2023-07-27

申请号：US18130326

申请日：2023-04-03

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Chia-ching Lin ,  Raseong Kim ,  Ashish Verma Penumatcha ,  Uygar Avci ,  Ian Young

IPC: H01L29/51 ,  H01L27/088 ,  H01L29/78 ,  H03H9/17 ,  H01L29/423

CPC classification number: H01L29/516 ,  H01L27/0886 ,  H01L29/7851 ,  H03H9/17 ,  H01L29/78391 ,  H01L29/42356

Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.

公开(公告)号：US20230155550A1

公开(公告)日：2023-05-18

申请号：US17530250

申请日：2021-11-18

Applicant: Intel Corporation

Inventor： Gary A. Allen ,  Tanay A. Gosavi ,  Raseong Kim ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC: H03B5/36 ,  H03H9/17

CPC classification number: H03B5/36 ,  H03H9/178 ,  H03L7/099

Abstract: In one embodiment, a piezo-resistive resonator device includes one or more drive transistors with source and drain regions in a first well and a sense transistor with source and drain regions in a second well of opposite polarity than the first well. The gates of the drive and sense transistor are connected to a first direct current (DC) source. The drain region of the sense transistor is connected to a second DC source, and the source and drain regions of the drive transistor are connected to an alternating current (AC) source.

公开(公告)号：US20200212193A1

公开(公告)日：2020-07-02

申请号：US16238419

申请日：2019-01-02

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Chia-ching Lin ,  Raseong Kim ,  Ashish Verma Penumatcha ,  Uygar Avci ,  Ian Young

IPC: H01L29/51 ,  H01L27/088 ,  H01L29/423 ,  H03H9/17 ,  H01L29/78

Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.

公开(公告)号：US20200162024A1

公开(公告)日：2020-05-21

申请号：US16192841

申请日：2018-11-16

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Raseong Kim ,  Sasikanth Manipatruni ,  Ian A. Young ,  Gary Alfred Allen ,  Tanay Gosavi

IPC: H03B5/24 ,  H01L29/78 ,  H01L27/06

Abstract: Embodiments may relate to a piezoresistive oscillator. The oscillator may include a fin field-effect transistor (FinFET) with a source electrode, a drain electrode, and a gate electrode. The oscillator may further include an electrical coupling coupled with the FinFET, wherein the electrical coupling electrically couples the gate electrode to the source electrode or the drain electrode. Other embodiments may be described or claimed.

公开(公告)号：US10522683B2

公开(公告)日：2019-12-31

申请号：US15962634

申请日：2018-04-25

Applicant: INTEL CORPORATION

Inventor： Raseong Kim ,  Uygar Avci ,  Ian Young

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/16 ,  H01L21/285 ,  H01L21/768 ,  H01L21/02

Abstract: An embodiment includes an apparatus comprising: a transistor including an epitaxial source, a channel, and an epitaxial drain; a fin that includes the channel, the channel including a long axis and a short axis; a source contact corresponding to the source; and a drain contact corresponding to the drain; wherein (a) an additional axis intersects each of the source contact, the source, the drain, and the drain contact, and (b) the additional axis is parallel to the long axis. Other embodiments are described herein.

公开(公告)号：US09294035B2

公开(公告)日：2016-03-22

申请号：US13994714

申请日：2013-03-28

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Raseong Kim ,  Rajashree Baskaran ,  Rajeev K. Dokania ,  Ian A. Young

IPC: H03B5/12 ,  H03B5/30 ,  H01L29/66 ,  H01L29/78

CPC classification number: H03B5/30 ,  H01L29/66795 ,  H01L29/7831 ,  H01L2924/13067 ,  H01L2924/13084

Abstract: An embodiment includes an oscillator comprising an amplifier formed on a substrate; a multiple gate resonant channel array, formed on the substrate, including: (a) transistors including fins, each of the fins having a channel between source and drain nodes, coupled to common source and drain contacts; and (b) common first and second tri-gates coupled to each of the fins and located between the source and drain contacts; wherein the fins mechanically resonate at a first frequency when one of the first and second tri-gates is periodically activated to produce periodic downward forces on the fins. Other embodiments include a non planar transistor with a channel between the source and drain nodes and a tri-gate on the fin; wherein the fin mechanically resonates when the first tri-gate is periodically activated to produce periodic downward forces on the fin. Other embodiments are described herein.

Abstract translation: 实施例包括：振荡器，包括形成在基板上的放大器; 形成在所述衬底上的多栅极共振沟道阵列包括：（a）包括鳍片的晶体管，每个鳍片在源极和漏极节点之间具有耦合到共源极和漏极触点的沟道; 和（b）共同的第一和第二三栅极，其耦合到每个散热片并且位于源极和漏极接触之间; 其中当第一和第二三门中的一个被周期性地激活以在翅片上产生周期性向下的力时，翅片以第一频率机械共振。 其他实施例包括在源极和漏极节点之间具有沟道的非平面晶体管和鳍上的三栅极; 其中当所述第一三栅极被周期性地激活以在所述散热片上产生周期性向下的力时，所述翅片机械谐振。 本文描述了其它实施例。

公开(公告)号：US12113117B2

公开(公告)日：2024-10-08

申请号：US18130326

申请日：2023-04-03

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Chia-ching Lin ,  Raseong Kim ,  Ashish Verma Penumatcha ,  Uygar Avci ,  Ian Young

IPC: H01L29/51 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H03H9/17

CPC classification number: H01L29/516 ,  H01L27/0886 ,  H01L29/42356 ,  H01L29/78391 ,  H01L29/7851 ,  H03H9/17

Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.

公开(公告)号：US20240113220A1

公开(公告)日：2024-04-04

申请号：US17958094

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Uygar E. Avci ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Jason C. Retasket ,  Shriram Shivaraman ,  Dominique A. Adams ,  Carly Rogan ,  Punyashloka Debashis ,  Brandon Holybee ,  Rachel A. Steinhardt ,  Sudarat Lee

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/20 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66 ,  H01L29/76

CPC classification number: H01L29/78391 ,  H01L21/0254 ,  H01L21/02568 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/516 ,  H01L29/66522 ,  H01L29/6684 ,  H01L29/66969 ,  H01L29/7606

Abstract: Technologies for a transistor with a thin-film ferroelectric gate dielectric are disclosed. In the illustrative embodiment, a transistor has a thin layer of scandium aluminum nitride (ScxAl1-xN) ferroelectric gate dielectric. The channel of the transistor may be, e.g., gallium nitride or molybdenum disulfide. In one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. In another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. Such a transistor can be used as a one-transistor memory cell.

公开(公告)号：US20240113212A1

公开(公告)日：2024-04-04

申请号：US17956296

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Tristan A. Tronic ,  Dominique A. Adams ,  Carly Rogan ,  Hai Li ,  Arnab Sen Gupta ,  Gauri Auluck ,  I-Cheng Tung ,  Brandon Holybee ,  Rachel A. Steinhardt ,  Punyashloka Debashis

IPC: H01L29/775 ,  H01L21/02 ,  H01L21/465 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L21/02565 ,  H01L21/02603 ,  H01L21/465 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66969

Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers, such as undoped semiconductor layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be preferentially etched away, leaving the doped semiconductor layers as fins for a ribbon FET. In another embodiment, an interlayer can be deposited on top of a semiconductor layer, and a ferroelectric layer can be deposited on the interlayer. The interlayer can bridge a gap in lattice parameters between the semiconductor layer and the ferroelectric layer.

公开(公告)号：US20240097031A1

公开(公告)日：2024-03-21

申请号：US17947071

申请日：2022-09-16

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Rachel A. Steinhardt ,  Brandon Holybee ,  Kevin P. O'Brien ,  Dmitri Evgenievich Nikonov ,  John J. Plombon ,  Ian Alexander Young ,  Raseong Kim ,  Carly Rogan ,  Dominique A. Adams ,  Arnab Sen Gupta ,  Marko Radosavljevic ,  Scott B. Clendenning ,  Gauri Auluck ,  Hai Li ,  Matthew V. Metz ,  Tristan A. Tronic ,  I-Cheng Tung

IPC: H01L29/78 ,  H01L29/51

CPC classification number: H01L29/78391 ,  H01L29/516

Abstract: In one embodiment, a transistor device includes a gate material layer on a substrate, a ferroelectric (FE) material layer on the gate material, a semiconductor channel material layer on the FE material layer, a first source/drain material on the FE material layer and adjacent the semiconductor channel material layer, and a second source/drain material on the FE material layer and adjacent the semiconductor channel material layer and on an opposite side of the semiconductor channel material layer from the first source/drain material. A first portion of the FE material layer is directly between the gate material and the first source/drain material, and a second portion of the FE material layer is directly between the gate material and the second source/drain material.