公开(公告)号：US12009026B2

公开(公告)日：2024-06-11

申请号：US17117795

申请日：2020-12-10

Applicant: Intel Corporation

Inventor： Clifford Ong ,  Yu-Lin Chao ,  Dmitri E. Nikonov ,  Ian Young ,  Eric A. Karl

IPC: G11C11/54 ,  G06F3/06 ,  G11C7/10 ,  G11C11/56 ,  G11C7/06 ,  G11C7/22

CPC classification number: G11C11/56 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0673 ,  G11C7/1051 ,  G11C7/1096 ,  G11C7/06 ,  G11C7/222

Abstract: Systems and methods for precision writing of weight values to a memory capable of storing multiple levels in each cell are disclosed. Embodiments include logic to compare an electrical parameter read from a memory cell with a base reference and an interval reference, and stop writing once the electrical parameter is between the base reference and the base plus the interval reference. The interval may be determined using a greater number of levels than the number of stored levels, to prevent possible overlap of read values of the electrical parameter due to memory device variations.

公开(公告)号：US20230253475A1

公开(公告)日：2023-08-10

申请号：US18130334

申请日：2023-04-03

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Chia-Ching Lin ,  Raseong Kim ,  Ashish Verma Penumatcha ,  Uygar Avci ,  Ian Young

IPC: H01L29/51 ,  H01L27/088 ,  H01L29/78 ,  H03H9/17 ,  H01L29/423

CPC classification number: H01L29/516 ,  H01L27/0886 ,  H01L29/7851 ,  H03H9/17 ,  H01L29/78391 ,  H01L29/42356

Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.

公开(公告)号：US11508903B2

公开(公告)日：2022-11-22

申请号：US16022094

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Angeline Smith ,  Ian Young ,  Kaan Oguz ,  Sasikanth Manipatruni ,  Christopher Wiegand ,  Kevin O'Brien ,  Tofizur Rahman ,  Noriyuki Sato ,  Benjamin Buford ,  Tanay Gosavi

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10

Abstract: An insertion layer for perpendicular spin orbit torque (SOT) memory devices between the SOT electrode and the free magnetic layer, memory devices and computing platforms employing such insertion layers, and methods for forming them are discussed. The insertion layer is predominantly tungsten and improves thermal stability and perpendicular magnetic anisotropy in the free magnetic layer.

公开(公告)号：US11416165B2

公开(公告)日：2022-08-16

申请号：US16160482

申请日：2018-10-15

Applicant: INTEL CORPORATION

Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young ,  Abhishek Sharma

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/1081 ,  G06N3/04 ,  G06F12/0802 ,  G06N3/063 ,  G06F12/0875 ,  G06F12/0897

Abstract: The present disclosure is directed to systems and methods of implementing a neural network using in-memory, bit-serial, mathematical operations performed by a pipelined SRAM architecture (bit-serial PISA) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. The bit-serial PISA circuitry is coupled to PISA memory circuitry via a relatively high-bandwidth connection to beneficially facilitate the storage and retrieval of layer weights by the bit-serial PISA circuitry during execution. Direct memory access (DMA) circuitry transfers the neural network model and input data from system memory to the bit-serial PISA memory and also transfers output data from the PISA memory circuitry to system memory circuitry. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of vector/tensor calculations without burdening the processor circuitry.

公开(公告)号：US20220199619A1

公开(公告)日：2022-06-23

申请号：US17133208

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Ashish Verma Penumatcha ,  Seung Hoon Sung ,  Jack Kavalieros ,  Uygar Avci ,  Tristan Tronic ,  Shriram Shivaraman ,  Devin Merrill ,  Tobias Brown-Heft ,  Kirby Maxey ,  Matthew Metz ,  Ian Young

IPC: H01L27/092 ,  H01L27/22 ,  H01L27/24 ,  H01L43/02 ,  H01L43/08 ,  H01L45/00 ,  H01L43/12

Abstract: A complementary metal oxide semiconductor (CMOS) transistor includes a first transistor with a first gate dielectric layer above a first channel, where the first gate dielectric layer includes Hf1-xZxO2, where 0.33

公开(公告)号：US20220115438A1

公开(公告)日：2022-04-14

申请号：US17070808

申请日：2020-10-14

Applicant: Intel Corporation

Inventor： Hai Li ,  Dmitri Nikonov ,  Chia-Ching Lin ,  Tanay Gosavi ,  Ian Young

IPC: H01L27/22 ,  H01F10/32

Abstract: A differential magnetoelectric spin-orbit (MESO) logic device is provided where two ports are used to connect the spin orbital module of the MESO device and a ferroelectric capacitor. In some examples, an insulating layer is added to decouple current paths.

公开(公告)号：US20210343856A1

公开(公告)日：2021-11-04

申请号：US17336149

申请日：2021-06-01

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Sou-Chi Chang ,  Chia-Ching Lin ,  Jack Kavalieros ,  Uygar Avci ,  Ian Young

IPC: H01L29/51 ,  H01L29/15 ,  H01L29/221 ,  H01L29/94

Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by providing tensile stress along a plane (e.g., x-axis) of a ferroelectric or anti-ferroelectric material of the ferroelectric/anti-ferroelectric based capacitor. Tensile stress is provided by a spacer comprising metal, semimetal, or oxide (e.g., metal or oxide of one or more of: Al, Ti, Hf, Si, Ir, or N). The tensile stress provides polar orthorhombic phase to the ferroelectric material and tetragonal phase to the anti-ferroelectric material. As such, memory window and reliability of the ferroelectric/anti-ferroelectric oxide thin film improves.

公开(公告)号：US20210305398A1

公开(公告)日：2021-09-30

申请号：US16833375

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Chia-Ching Lin ,  Nazila Haratipour ,  Tanay Gosavi ,  I-Cheng Tung ,  Seung Hoon Sung ,  Ian Young ,  Jack Kavalieros ,  Uygar Avci ,  Ashish Verma Penumatcha

IPC: H01L29/51 ,  H01L29/92 ,  H01L29/24

Abstract: A capacitor device includes a first electrode having a first metal alloy or a metal oxide, a relaxor ferroelectric layer adjacent to the first electrode, where the ferroelectric layer includes oxygen and two or more of lead, barium, manganese, zirconium, titanium, iron, bismuth, strontium, neodymium, potassium, or niobium and a second electrode coupled with the relaxor ferroelectric layer, where the second electrode includes a second metal alloy or a second metal oxide.

公开(公告)号：US10885963B2

公开(公告)日：2021-01-05

申请号：US16221175

申请日：2018-12-14

Applicant: Intel Corporation

Inventor： Dmitri Nikonov ,  Ilya Karpov ,  Ian Young

IPC: G11C11/22 ,  H01L27/1159 ,  G06N3/02 ,  G11C11/54

Abstract: An embodiment includes an apparatus comprising: a first layer and a second layer; a first gate including first gate portions and a second gate including second gate portions; wherein the first layer: (a) is monolithic, (b) is between the first gate portions and is also between the second gate portions, and (c) includes a semiconductor material; wherein the second layer: (a) is between the first layer and at least one of the first gate portions and is also between the first layer and at least one of the second gate portions, and (b) includes oxygen and at least one of hafnium, silicon, yttrium, zirconium, barium, titanium, lead, or combinations thereof; wherein (a) a first plane intersects the first gate portions and the first and second layers, and (b) a second plane intersects the second gate portions and the first and second layers. Other embodiments are described herein.

公开(公告)号：US10600957B2

公开(公告)日：2020-03-24

申请号：US15519810

申请日：2014-12-18

Applicant: INTEL CORPORATION

Inventor： David Michalak ,  Sasikanth Manipatruni ,  James Clarke ,  Dmitri Nikonov ,  Ian Young

IPC: H01L43/10 ,  G01R33/12 ,  G11B5/39 ,  H01L43/08 ,  H01L43/12 ,  G01D5/20 ,  H01L43/02

Abstract: Described is a method comprising: forming a magnet on a substrate or a template, the magnet having an interface; and forming a first layer of non-magnet conductive material on the interface of the magnet such that the magnet and the layer of non-magnet conductive material are formed in-situ. Described is an apparatus comprising: a magnet formed on a substrate or a template, the magnet being formed under crystallographic, electromagnetic, or thermodynamic conditions, the magnet having an interface; and a first layer of non-magnet conductive material formed on the interface of the magnet such that the magnet and the layer of non-magnet conductive material are formed in-situ.