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公开(公告)号：US10740281B2
公开(公告)日：2020-08-11
申请号：US16103798
申请日：2018-08-14
Applicant: INTEL CORPORATION
Inventor： Varghese George , Sanjeev S. Jahagirdar , Deborah T. Marr
IPC: G06F15/80 , G06F1/3206 , G06F1/3293 , G06F9/50 , G06F1/3296 , G06F13/40
Abstract: A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating frequency.
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公开(公告)号：US20190130639A1
公开(公告)日：2019-05-02
申请号：US16234463
申请日：2018-12-27
Applicant: Intel Corporation
Inventor： Jill Boyce , Soethiha Soe , Selva Panneer , Adam Lake , Nilesh Jain , Deepak Vembar , Glen J. Anderson , Varghese George , Carl Marshall , Scott Janus , Saurabh Tangri , Karthik Veeramani , Prasoonkumar Surti
Abstract: Embodiments are directed to neural network processing for multi-object three-dimensional (3D) modeling. An embodiment of a computer-readable storage medium includes executable computer program instructions for obtaining data from multiple cameras, the data including multiple images, and generating a 3D model for 3D imaging based at least in part on the data from the cameras, wherein generating the 3D model includes one or more of performing processing with a first neural network to determine temporal direction based at least in part on motion of one or more objects identified in an image of the multiple images or performing processing with a second neural network to determine semantic content information for an image of the multiple images.
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公开(公告)号：US10049080B2
公开(公告)日：2018-08-14
申请号：US15431527
申请日：2017-02-13
Applicant: Intel Corporation
Inventor： Varghese George , Sanjeev S. Jahagirdar , Deborah T. Marr
Abstract: A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating frequency.
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公开(公告)号：US09874925B2
公开(公告)日：2018-01-23
申请号：US14966708
申请日：2015-12-11
Applicant: Intel Corporation
Inventor： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
IPC: G06F1/32 , G06F12/08 , G06F11/14 , G06F12/084 , G06F12/0875 , G11C7/10 , G06F9/44
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
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公开(公告)号：US09841807B2
公开(公告)日：2017-12-12
申请号：US14959549
申请日：2015-12-04
Applicant: Intel Corporation
Inventor： Sanjeev Jahagirdar , Varghese George , John Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
IPC: G06F1/32 , G06F11/14 , G06F12/084 , G06F12/0875 , G11C7/10 , G06F9/44
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
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Patent Agency Ranking
公开(公告)号：US09274592B2
公开(公告)日：2016-03-01
申请号：US14141926
申请日：2013-12-27
Applicant: INTEL CORPORATION
Inventor： Sanjeev Jahagirdar , Varghese George , Jose Allarey
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/3275 , G06F12/0811 , G06F12/0831 , G06F12/084 , G06F2212/1024 , G06F2212/1028 , G06F2212/1048 , Y02D10/13 , Y02D10/14 , Y02D50/20
Abstract: A technique to retain cached information during a low power mode, according to at least one embodiment. In one embodiment, information stored in a processor's local cache is saved to a shared cache before the processor is placed into a low power mode, such that other processors may access information from the shared cache instead of causing the low power mode processor to return from the low power mode to service an access to its local cache.
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公开(公告)号：US09223390B2
公开(公告)日：2015-12-29
申请号：US14496345
申请日：2014-09-25
Applicant: Intel Corporation
Inventor： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
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公开(公告)号：US20150169043A1
公开(公告)日：2015-06-18
申请号：US14630909
申请日：2015-02-25
Applicant: Intel Corporation
Inventor： Sanjeev Jahagirdar , Varghese George , John Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
IPC: G06F1/32
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
Abstract translation: 本发明的实施例涉及一种用于零电压处理器睡眠状态的方法和装置。 处理器可以包括专用高速缓存存储器。 电压调节器可以耦合到处理器以向处理器提供工作电压。 在处理器转换到零电压电源管理状态期间，电压调节器施加到处理器的工作电压可以减小到大约零，并且与处理器相关联的状态变量可以被保存到专用高速缓冲存储器。
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公开(公告)号：US20150058667A1
公开(公告)日：2015-02-26
申请号：US14496345
申请日：2014-09-25
Applicant: Intel Corporation
Inventor： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
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公开(公告)号：US20250166114A1
公开(公告)日：2025-05-22
申请号：US18967123
申请日：2024-12-03
Applicant: Intel Corporation
Inventor： Abhishek Appu , Subramaniam Maiyuran , Mike Macpherson , Fangwen Fu , Jiasheng Chen , Varghese George , Vasanth Ranganathan , Ashutosh Garg , Joydeep Ray
IPC: G06T1/20 , G06F7/544 , G06F9/30 , G06F9/38 , G06F9/50 , G06F12/0806 , G06F15/80 , G06F17/16 , G06N3/048 , G06N3/08 , G06N3/084
Abstract: Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides for data aware sparsity via compressed bitstreams. One embodiment provides for block sparse dot product instructions. One embodiment provides for a depth-wise adapter for a systolic array.
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