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公开(公告)号：US11101321B2
公开(公告)日：2021-08-24
申请号：US15572035
申请日：2015-09-06
Inventor： Writam Banerjee , Ming Liu , Qi Liu , Hangbing Lv , Haitao Sun , Kangwei Zhang
IPC: H01L45/00 , H01L27/24 , H01L27/105 , G11C13/00
Abstract: A nonvolatile resistive switching memory comprising an insulating substrate, a lower electrode, a lower graphene barrier layer, a resistive switching functional layer, an upper graphene barrier layer, and an upper electrode, wherein the lower and/or the upper graphene barrier layer is/are capable of preventing the metal ions/atoms in the lower/upper metal electrode from diffusing into the resistive switching functional layer under an applied electric field. According to the nonvolatile resistive switching memory device of the present invention and manufacturing method thereof, a monolayer or multilayer graphene film as a metal ions/atoms barrier layer is inserted between the upper/lower metal electrode and the resistive switching functional layer, which is capable of preventing the metal ions/atoms in the lower/upper metal electrode from diffusing into the resistive switching functional layer during the programming or erasing process of the resistive switching device, thereby improving the reliability of the device.
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公开(公告)号：US20200176674A1
公开(公告)日：2020-06-04
申请号：US16786346
申请日：2020-02-10
Inventor： Qing Luo , Hangbing Lv , Ming Liu , Xiaoxin Xu , Cheng Lu
IPC: H01L45/00
Abstract: The present disclosure provides a 1S1R memory integrated structure and a method for fabricating the same, wherein the 1S1R memory integrated structure includes: a word line metal, a resistive material layer, a selector lower electrode, a selector material layer, a selector upper electrode, an interconnection wire, and a bit line metal; wherein the selector material layer is in a shape of a groove, and the selector upper electrode is formed in the groove. According to the 1S1R memory integrated structure and its fabricating method in the present disclosure, by the change of the integrated position of the selector, the device area of the selector is much larger than the device area of the memory, which significantly reduces the requirement for the on-state current density of the selector.
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公开(公告)号：US10418549B2
公开(公告)日：2019-09-17
申请号：US16064116
申请日：2016-08-12
Inventor： Nianduan Lu , Pengxiao Sun , Ling Li , Ming Liu , Qi Liu , Hangbing Lv , Shibing Long
Abstract: A method for evaluating the thermal effects of 3D RRAM arrays and reducing thermal crosstalk, including the following steps: Step 1: calculating the temperature distribution in the array through 3D Fourier heat conduction equation; Step 2, selecting a heat transfer mode; Step 3, selecting an appropriate array structure; Step 4, analyzing the effect of position of programming device in the array on the temperature; Step 5, analyzing the thermal crosstalk effect in the array; Step 6, evaluating thermal effects and thermal crosstalk; Step 7, changing the array structure or modify operating parameters based on the evaluation results to reduce the thermal crosstalk. According to the method of the present invention, the influence of the position of the device on the temperature is analyzed according to the heat transfer mode of the 3D RRAM array, the thermal effect and the thermal crosstalk are evaluated, and the appropriate array structure and operating parameters are selected according to the evaluation result, which effectively improves the thermal stability of the device.
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公开(公告)号：US10297748B2
公开(公告)日：2019-05-21
申请号：US15539608
申请日：2014-12-26
Inventor： Hangbing Lv , Ming Liu , Qi Liu , Shibing Long
Abstract: There is provided a three-terminal atomic switching device and a method of manufacturing the same, which belongs to the field of microelectronics manufacturing and memory technology. The three-terminal atomic switching device includes: a stack structure including a source terminal and a drain terminal; a vertical trench formed by etching the stack structure; an M8XY6 channel layer formed on an inner wall and a bottom of the vertical trench; and a control terminal formed on a surface of the M8XY6 channel layer, wherein the control terminal fills the vertical trench. The source terminal resistance and the drain terminal resistance are controlled by the control terminal. The invention is based on the three-terminal atomic switching device, and realizes high switching ratio characteristic, simple structure, easy integration, high density and low cost due to high non-linearity of the source-drain resistance with respect to the control terminal voltage, and thus can be used in a gated device in a cross-array structure to inhibit a crosstalk phenomenon caused by the leakage current. The three-terminal atomic switching device proposed by the invention is suitable for a planar stacked cross-array structure and a vertical cross-array structure, so as to realize high-density three-dimensional storage.
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公开(公告)号：US20180026183A1
公开(公告)日：2018-01-25
申请号：US15546212
申请日：2015-05-14
Inventor： Qi Liu , Ming Liu , Haitao Sun , Keke Zhang , Shibing Long , Hangbing Lv , Writam Banerjee , Kangwei Zhang
IPC: H01L45/00
CPC classification number: H01L45/1246 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/146 , H01L45/16
Abstract: A nonvolatile resistive switching memory, comprising an inert metal electrode, a resistive switching functional layer, and an easily oxidizable metal electrode, and characterized in that: a graphene barrier layer is inserted between the inert metal electrode and the resistive switching functional layer, which is capable of preventing the easily oxidizable metal ions from migrating into the inert metal electrode through the resistive switching functional layer under the action of electric field during the programming of the device. The manufacturing method therefore comprises adding a monolayer or multilayer graphene thin film between the inert electrode and the solid-state electrolyte resistive switching functional layer which services as a metal ion barrier layer to stop electrically-conductive metal filaments formed in the resistive switching layer from diffusing into the inert electrode layer during a RRAM device programming process, eliminating erroneous programming phenomenon occurring during the erasing process, improving device reliability.
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Patent Agency Ranking
公开(公告)号：US20180019393A1
公开(公告)日：2018-01-18
申请号：US15546218
申请日：2015-05-14
Inventor： Qi Liu , Ming Liu , Haltao Sun , Hangbing Lv , Shibing Long , Writam Banerjee , Kangwei Zhang
IPC: H01L45/00
CPC classification number: H01L45/143 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/144 , H01L45/146 , H01L45/1608
Abstract: A nonvolatile resistive switching memory includes an inert metal electrode, a resistive switching functional layer, and an easily oxidizable metal electrode. A graphene intercalation layer with nanopores, interposed between the easily oxidizable metal electrode and the resistive switching functional layer, is capable of controlling the metal ions, which are formed by the oxidation of the easily oxidizable metal electrode during the programming of the device, and only enter into the resistive switching functional layer through the position of the nanopores. Further, the graphene intercalation layer with nanopores is capable of blocking the diffusion of the metal ions, making the metal ions, which are formed after the oxidation of the easily oxidizable metal electrode, enter into the resistive switching functional layer only through the position of the nanopores during the programming of the device, thereby controlling the growing position of conductive filament.
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公开(公告)号：US20170018424A1
公开(公告)日：2017-01-19
申请号：US15300925
申请日：2014-04-17
Inventor： Dongmei Li , Lei Zhou , Shengfa Liang , Xiaojing Li , Hao Zhang , Changqing Xie , Ming Liu
CPC classification number: H01L21/02082 , B08B3/12 , C11D3/3947 , C11D7/06 , C11D7/08 , C11D7/10 , C11D11/0047 , C11D11/007 , H01L21/02052
Abstract: The present disclosure provides a method for cleaning a lanthanum gallium silicate wafer which comprises the following steps: at a step of 1, a cleaning solution constituted of phosphorous acid, hydrogen peroxide and deionized water is utilized to clean the lanthanum gallium silicate wafer with a megahertz sound wave; at a step of 2, the cleaned lanthanum gallium silicate wafer is rinsed and dried by spinning; at a step of 3, a cleaning solution constituted of ammonia, hydrogen peroxide and deionized water is utilized to clean the lanthanum gallium silicate wafer with the megahertz sound wave; at a step of 4, the cleaned lanthanum gallium silicate wafer is rinsed and dried by spinning; and at a step of 5, the rinsed and dried wafer is placed in an oven to be baked. The present invention shortens a period of acidic cleaning process and prolongs a period of alkaline cleaning and utilizes a more effective cleaning with megahertz sound wave to replace the conventional ultrasonic cleaning to solve the issue of cleaning the lanthanum gallium silicate wafer after a cutting process and to improve surface cleanliness of the lanthanum gallium silicate wafer to get a better cleaning effect.
Abstract translation: 本公开内容提供了一种用于清洁镓酸镓镧晶圆的方法，其包括以下步骤：在步骤1，使用由亚磷酸，过氧化氢和去离子水构成的清洁溶液来清洁硅酸镓镧镓晶圆 声波; 在步骤2中，将经清洗的硅酸镓镧硅酸盐晶片通过旋转进行漂洗和干燥; 在步骤3中，使用由氨，过氧化氢和去离子水组成的清洁溶液来用兆赫声波清洗硅酸镓镧晶圆; 在步骤4中，将清洁的硅酸镓镧晶片漂洗并通过纺丝干燥; 并且在步骤5中，将经漂洗并干燥的晶片放置在烘箱中烘烤。 本发明缩短了一段时间的酸性清洗工艺，延长了碱性清洗时间，并利用更频繁的清洁用兆赫声波来代替传统的超声波清洗，以解决在切割过程之后清洗硅酸镓镧晶片的问题， 提高镧硅酸镓晶片的表面清洁度，以获得更好的清洁效果。
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28.发明授权Method for collecting signal with sampling frequency lower than Nyquist frequency 有权采样频率低于奈奎斯特频率的信号采集方法公开(公告)号：US09455741B2
公开(公告)日：2016-09-27
申请号：US14805868
申请日：2015-07-22
Inventor： Dongmei Li , Xiaojing Li , Shengfa Liang , Hao Zhang , Qing Luo , Changqing Xie , Ming Liu
CPC classification number: H03M7/3062 , H03M7/30 , H04L27/2642
Abstract: A method for collecting a signal with a frequency lower than a Nyquist frequency includes, by a data transmitting end, selecting a suitable transformation base matrix for an input signal, deriving a sparse representation of the signal using the transformation base matrix to determine a sparsity of the signal, calculating a number M of compressive sampling operations according to the sparsity, sampling the signal with fNYQ/M using M channels, and integrating sampling values of each channel to obtain M measurement values. A reconstruction end reconstructs an original signal by solving optimization problems. Based on theory, compressive sampling can be performed on a sparse signal or a signal represented in a sparse manner with a frequency much lower than the Nyquist frequency, overcoming restrictions of the typical Nyquist sampling theorem. The method can be implemented simply and decrease pressure on data collection, storage, transmission and processing.
Abstract translation: 收集频率低于奈奎斯特频率的信号的方法包括：通过数据发送端，为输入信号选择合适的变换基矩阵，使用变换基矩阵导出信号的稀疏表示，以确定稀疏度 信号，根据稀疏度计算M个压缩采样操作，使用M个通道对fNYQ / M采样信号，并对每个通道的采样值进行积分以获得M个测量值。 重建结束通过解决优化问题重建原始信号。 基于理论，可以对稀疏信号或以稀疏方式表示的信号执行压缩采样，频率远低于奈奎斯特频率，克服典型奈奎斯特采样定理的限制。 该方法可以简单实现，减少数据收集，存储，传输和处理的压力。
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29.发明授权Vertical channel-type 3D semiconductor memory device and method for manufacturing the same 有权垂直通道型3D半导体存储器件及其制造方法公开(公告)号：US09437609B2
公开(公告)日：2016-09-06
申请号：US14581990
申请日：2014-12-23
Inventor： Zongliang Huo , Ming Liu
IPC: H01L29/792 , H01L27/115 , H01L21/764 , H01L29/788 , H01L21/02 , H01L21/28 , H01L21/311 , H01L29/04 , H01L29/16 , H01L29/161 , H01L29/20 , H01L29/201 , H01L29/49 , H01L29/51
CPC classification number: H01L27/11582 , H01L21/0217 , H01L21/02181 , H01L21/02532 , H01L21/02546 , H01L21/02592 , H01L21/02595 , H01L21/02667 , H01L21/28273 , H01L21/28282 , H01L21/31111 , H01L21/32133 , H01L21/324 , H01L21/764 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L29/04 , H01L29/0649 , H01L29/16 , H01L29/161 , H01L29/20 , H01L29/201 , H01L29/4916 , H01L29/517 , H01L29/518 , H01L29/7883 , H01L29/7889 , H01L29/7926
Abstract: A vertical channel-type 3D semiconductor memory device and a method for manufacturing the same are disclosed. In one aspect, the device includes a multi-layer film formed by depositing alternating layers of insulation and an electrode material on a substrate. The device also includes through-holes formed by etching the film to the substrate. The device also includes gate stacks formed by depositing barrier storage and a tunnel layers in sequence on inner walls of the through-holes. The device also includes hollow channels formed by depositing a channel material on the tunnel layer. The device also includes drains for bit-line connection in top portions of the hollow channels. The device also includes sources formed in contact regions between through-holes and the substrate in bottom portions of the hollow channels.
Abstract translation: 公开了一种垂直沟道型3D半导体存储器件及其制造方法。 一方面，该装置包括通过在衬底上沉积交替的绝缘层和电极材料形成的多层膜。 该器件还包括通过将膜蚀刻到衬底而形成的通孔。 该装置还包括通过在通孔的内壁依次沉积阻挡层和隧道层而形成的栅堆叠。 该装置还包括通过在隧道层上沉积沟道材料形成的中空通道。 该装置还包括用于在中空通道顶部的位线连接的排水口。 该装置还包括形成在中空通道的底部中的通孔和基板之间的接触区域中的源。
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30.发明申请VERTICAL CHANNEL-TYPE 3D SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权垂直通道型3D半导体存储器件及其制造方法公开(公告)号：US20150179661A1
公开(公告)日：2015-06-25
申请号：US14581990
申请日：2014-12-23
Inventor： Zongliang Huo , Ming Liu
IPC: H01L27/115 , H01L29/792 , H01L29/16 , H01L29/161 , H01L29/20 , H01L21/02 , H01L29/49 , H01L29/51 , H01L29/04 , H01L21/28 , H01L21/311 , H01L29/788 , H01L29/201
CPC classification number: H01L27/11582 , H01L21/0217 , H01L21/02181 , H01L21/02532 , H01L21/02546 , H01L21/02592 , H01L21/02595 , H01L21/02667 , H01L21/28273 , H01L21/28282 , H01L21/31111 , H01L21/32133 , H01L21/324 , H01L21/764 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L29/04 , H01L29/0649 , H01L29/16 , H01L29/161 , H01L29/20 , H01L29/201 , H01L29/4916 , H01L29/517 , H01L29/518 , H01L29/7883 , H01L29/7889 , H01L29/7926
Abstract: A vertical channel-type 3D semiconductor memory device and a method for manufacturing the same are disclosed. In one aspect, the device includes a multi-layer film formed by depositing alternating layers of insulation and an electrode material on a substrate. The device also includes through-holes formed by etching the film to the substrate. The device also includes gate stacks formed by depositing barrier storage and a tunnel layers in sequence on inner walls of the through-holes. The device also includes hollow channels formed by depositing a channel material on the tunnel layer. The device also includes drains for bit-line connection in top portions of the hollow channels. The device also includes sources formed in contact regions between through-holes and the substrate in bottom portions of the hollow channels.
Abstract translation: 公开了一种垂直沟道型3D半导体存储器件及其制造方法。 一方面，该装置包括通过在衬底上沉积交替的绝缘层和电极材料形成的多层膜。 该器件还包括通过将膜蚀刻到衬底而形成的通孔。 该装置还包括通过在通孔的内壁依次沉积阻挡层和隧道层而形成的栅堆叠。 该装置还包括通过在隧道层上沉积沟道材料形成的中空通道。 该装置还包括用于在中空通道顶部的位线连接的排水口。 该装置还包括形成在中空通道的底部中的通孔和基板之间的接触区域中的源。
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