公开(公告)号：US20170169539A1

公开(公告)日：2017-06-15

申请号：US15445852

申请日：2017-02-28

Applicant: INTEL CORPORATION

Inventor： Peter L. Doyle ,  Jeffery S. Boles ,  Arthur D. Hunter, JR. ,  Altug Koker ,  Aditya Navale

IPC: G06T1/60 ,  G06T15/00 ,  G06T15/10 ,  G06T1/20

CPC classification number: G06T15/10 ,  G06T11/40 ,  G06T15/005 ,  G06T2210/52

Abstract: Systems, apparatus and methods are described including distributing batches of geometric objects to a multi-core system, at each processor core, performing vertex processing and geometry setup processing on the corresponding batch of geometric objects, storing the vertex processing results shared memory accessible to all of the cores, and storing the geometry setup processing results in local storage. Each particular core may then perform rasterization using geometry setup results obtained from local storage within the particular core and from local storage of at least one of the other processor cores.

公开(公告)号：US09626735B2

公开(公告)日：2017-04-18

申请号：US14124845

申请日：2013-06-24

Applicant: Intel Corporation

Inventor： Altug Koker ,  Aditya Navale

IPC: G06T1/60 ,  G09G5/393 ,  G06F12/0802 ,  G09G5/36

CPC classification number: G06T1/60 ,  G06F12/0802 ,  G06F2212/455 ,  G09G5/363 ,  G09G5/393 ,  G09G2360/121 ,  G09G2360/122

Abstract: Systems and methods may provide for identifying a tile associated with an image and ordering an entirety of the tile into a linear stream of pages associated with a frame buffer. Additionally, the linear stream of pages may be allocated to a cache. In one example, the linear stream of pages is allocated to the cache in accordance with a fixed set selection policy of the cache.

公开(公告)号：US09390462B2

公开(公告)日：2016-07-12

申请号：US13851400

申请日：2013-03-27

Applicant: Intel Corporation

Inventor： Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Aditya Navale

IPC: G06T1/60 ,  G06F12/10 ,  G06F9/48

CPC classification number: G06T1/60 ,  G06F9/485 ,  G06F12/1009 ,  G06F12/128 ,  G06T1/20

Abstract: An electronic device is described herein. The electronic device may include a page walker module to receive a page request of a graphics processing unit (GPU). The page walker module may detect a page fault associated with the page request. The electronic device may include a controller, at least partially comprising hardware logic. The controller is to monitor execution of the page request having the page fault. The controller determines whether to suspend execution of a work item at the GPU associated with the page request having the page fault, or to continue execution of the work item based on factors associated with the page request.

Abstract translation: 本文描述了一种电子设备。 电子设备可以包括页面助行器模块，用于接收图形处理单元（GPU）的页面请求。 页面助行器模块可以检测与页面请求相关联的页面错误。 电子设备可以包括至少部分地包括硬件逻辑的控制器。 控制器将监视具有页面错误的页面请求的执行。 控制器确定是否在与具有页面错误的页面请求相关联的GPU处挂起工作项的执行，或者基于与页面请求相关联的因素来继续执行工作项。

公开(公告)号：US20160147668A1

公开(公告)日：2016-05-26

申请号：US14963518

申请日：2015-12-09

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Aditya Navale ,  Wishwesh Gandhi

IPC: G06F12/10 ,  G06F9/455 ,  G06F9/44

CPC classification number: G06F12/1009 ,  G06F9/4401 ,  G06F9/4403 ,  G06F9/4411 ,  G06F9/45533 ,  G06F9/45558 ,  G06F12/109 ,  G06F13/28 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2212/152 ,  G06T1/60

Abstract: A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.

公开(公告)号：US20230306551A1

公开(公告)日：2023-09-28

申请号：US17702301

申请日：2022-03-23

Applicant: Intel Corporation

Inventor： Vidhya Krishnan ,  Niranjan Cooray ,  David Puffer ,  Ronald Silvas ,  Durgaprasad Bilagi ,  Aditya Navale

IPC: G06T1/20 ,  G06F12/02 ,  G06T1/60 ,  G06T9/00

CPC classification number: G06T1/20 ,  G06F12/0223 ,  G06T1/60 ,  G06T9/00 ,  G06F2212/401

Abstract: Described herein is a graphics processor comprising a processing resource configured to perform processing operations, a codec configured to compress and decompress data associated with the processing operations, and circuitry configured to calculate a metadata address for a compressed surface based on a flat virtual memory address mapping between the address of the compressed surface and the metadata address. The compressed surface is to store data associated with a processing operation to be performed by the processing resource and the metadata address is a virtual address that stores compression metadata for the compressed surface. The circuitry can configure the codec to access the compressed surface based on the compression metadata.

公开(公告)号：US20230298125A1

公开(公告)日：2023-09-21

申请号：US17827444

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： Hema Chand Nalluri ,  Jeffery S. Boles ,  David Cowperthwaite ,  Aditya Navale ,  Prasoonkumar Surti ,  Arthur Hunter ,  Vasanth Ranganathan ,  Joydeep Ray ,  David Puffer ,  Ankur Shah ,  Vidhya Krishnan ,  Kritika Bala ,  Aravindh Anantaraman ,  Michael Apodaca ,  Kenneth Daxer

IPC: G06T1/20 ,  G06T15/00 ,  G06T1/60 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06T1/20 ,  G06T15/005 ,  G06T1/60 ,  G06F9/4881 ,  G06F9/5061 ,  G06F9/505 ,  G06T2200/16

Abstract: Described herein is a partitionable graphics processor having multiple render front ends. The partitions of the graphics processor maintain render functionality when partitioned and enable fault isolation and independent multi-client rendering.

公开(公告)号：US20230297440A1

公开(公告)日：2023-09-21

申请号：US17827373

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： David Cowperthwaite ,  Kenneth Daxer ,  Jeffery S. Boles ,  Hema Chand Nalluri ,  Aditya Navale ,  Prasoonkumar Surti ,  Arthur Hunter ,  Vasanth Ranganathan ,  Joydeep Ray ,  David Puffer ,  Aravindh Anantaraman ,  Ankur Shah ,  Vidhya Krishnan ,  Kritika Bala

IPC: G06F9/50 ,  G06T1/20

CPC classification number: G06F9/5077 ,  G06F9/5016 ,  G06T1/20

Abstract: Described herein is a partitionable graphics processor having a plurality of flexibly partitioned processing resources. One embodiment provides a graphics processor comprising a plurality of processing resources configurable to be flexibly partitioned into a plurality of resource partitions and circuitry to compose multiple graphics processor device partitions from the plurality of resource partitions. The multiple graphics processor device partitions are configurable to be asymmetrically composed of different types of functional units.

公开(公告)号：US20230297421A1

公开(公告)日：2023-09-21

申请号：US17827346

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： David Cowperthwaite ,  Kenneth Daxer ,  Aditya Navale ,  Prasoonkumar Surti ,  Arthur Hunter ,  Hema Chand Nalluri ,  Jeffery S. Boles ,  Vasanth Ranganathan ,  Joydeep Ray ,  David Puffer ,  Aravindh Anantaraman ,  Ankur Shah ,  Vidhya Krishnan ,  Kritika Bala ,  Michael Apodaca

IPC: G06F9/48 ,  G06T1/60 ,  G06T1/20 ,  G06F9/50

CPC classification number: G06F9/4881 ,  G06T1/60 ,  G06T1/20 ,  G06F9/5038 ,  G06F9/5055

Abstract: Described herein is a partitional graphics processor having multiple hard partitions with separate software execution and fault domains. One embodiment provides a graphics processor comprising a system interface and a plurality of graphics processing resources coupled with the system interface. The plurality of graphics processing resources is configurable to be partitioned into a plurality of isolated device partitions, each isolated device partition configured for fault isolation and independent concurrent execution of workloads associated with a plurality of clients, and the system interface is configured to present each of the plurality of isolated device partitions as a virtual function.

公开(公告)号：US20220138286A1

公开(公告)日：2022-05-05

申请号：US17133336

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： David Zage ,  Scott Janus ,  Ned M. Smith ,  Vidhya Krishnan ,  Siddhartha Chhabra ,  Rajesh Poornachandran ,  Tomer Levy ,  Julien Carreno ,  Ankur Shah ,  Ronald Silvas ,  Aravindh Anantaraman ,  David Puffer ,  Vedvyas Shanbhogue ,  David Cowperthwaite ,  Aditya Navale ,  Omer Ben-Shalom ,  Alex Nayshtut ,  Xiaoyu Ruan

IPC: G06F21/10 ,  G06F21/60 ,  G06T1/20 ,  G06F9/455

Abstract: Systems, apparatuses and methods may provide for encryption based technology. Data may be encrypted locally with a graphics processor with encryption engines. The graphics processor components may be verified with a root-of-trust and based on collection of claims. The graphics processor may further be able to modify encrypted data from a non-pageable format to a pageable format. The graphics processor may further process data associated with a virtual machine based on a key that is known by the virtual machine and the graphics processor.

公开(公告)号：US11321262B2

公开(公告)日：2022-05-03

申请号：US17014023

申请日：2020-09-08

Applicant: Intel Corporation

Inventor： Hema Chand Nalluri ,  Ankur Shah ,  Joydeep Ray ,  Aditya Navale ,  Altug Koker ,  Murali Ramadoss ,  Niranjan L. Cooray ,  Jeffery S. Boles ,  Aravindh Anantaraman ,  David Puffer ,  James Valerio ,  Vasanth Ranganathan

IPC: G06F9/52 ,  G06F12/14 ,  G06F13/40 ,  G06F13/16 ,  G06F12/0888 ,  G06F12/0837 ,  G06F9/30

Abstract: An apparatus to facilitate memory barriers is disclosed. The apparatus comprises an interconnect, a device memory, a plurality of processing resources, coupled to the device memory, to execute a plurality of execution threads as memory data producers and memory data consumers to a device memory and a system memory and fence hardware to generate fence operations to enforce data ordering on memory operations issued to the device memory and a system memory coupled via the interconnect.