公开(公告)号：US10275247B2

公开(公告)日：2019-04-30

申请号：US14672156

申请日：2015-03-28

Applicant: Intel Corporation

Inventor： Asit K. Mishra ,  Deborah T. Marr

IPC: G06F9/30

Abstract: Methods and apparatuses relating to accelerating vector multiplication. In one embodiment, an apparatus includes a first buffer to store a first cache line of indices for elements of a first vector, a second buffer to store a second cache line of indices for elements of a second vector, a comparison unit to compare each index of the first cache line of indices with each index of the second cache line of indices, a plurality of multipliers to each multiply an element from the first vector and an element from the second vector for an index match from the comparison unit to produce a product, and an adder to add together the product from each of the plurality of multipliers.

公开(公告)号：US10198264B2

公开(公告)日：2019-02-05

申请号：US14969864

申请日：2015-12-15

Applicant: Intel Corporation

Inventor： Asit K. Mishra ,  Deborah T. Marr ,  Jong Soo Park ,  Nadathur Rajagopalan Satish ,  Mikhail Smelyanskiy ,  Michael Anderson ,  Mostofa Ali Patwary ,  Narayanan Sundaram ,  Sheng Li

IPC: G06F9/30

Abstract: A processing device includes a sorting module, which adds to each of a plurality of elements a position value of a corresponding position in a register rest resulting in a plurality of transformed elements in corresponding positions. The plurality of elements include a plurality of bits. The sorting module compares each of the plurality of transformed elements to itself and to one another. The sorting module also assigns one of an enabled or disabled indicator to each of the plurality of the transformed elements based on the comparison. The sorting module further counts a number of the enabled indicators assigned to each of the plurality of the transformed elements to generate a sorted sequence of the plurality of elements.

公开(公告)号：US09996361B2

公开(公告)日：2018-06-12

申请号：US14757609

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Asit K. Mishra ,  Kshitij A. Doshi ,  Elmoustapha Ould-Ahmed-Vall ,  Deborah T. Marr

IPC: G06F9/315 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3889 ,  G06F9/30 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30112 ,  G06F9/3861 ,  G06F9/3887

Abstract: A processor comprises a first register to store a plurality of data items at a plurality of positions within the first register, a second register, and an execution unit, operatively coupled to the first register and the second register, the execution unit comprising a logic circuit implementing a sort instruction for sorting the plurality of data items stored in the first register in an order of data item values, and storing, in the second register, a plurality of indices, wherein each index identifies a position associated with a data item stored in the first register prior to the sorting.

公开(公告)号：US20170185412A1

公开(公告)日：2017-06-29

申请号：US14757995

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Asit K. Mishra ,  Kshitij A. Doshi ,  Elmoustapha Ould-Ahmed-Vall ,  Deborah T. Marr

IPC: G06F9/38 ,  G06F15/80 ,  G06F9/30

CPC classification number: G06F9/3887 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30098 ,  G06F15/8007

Abstract: Single Instruction, Multiple Data (SIMD) technologies are described. A method of performing a key value lookup instruction may include storing a vector of keys to a first register and storing a vector of values corresponding to the keys to a second register. A processor may receive an instruction to perform a key value lookup instruction including a vector of key input elements. The processor may compare each key input element to each key to determine matching keys. The processor may then store values corresponding to the matching keys to an output vector in the position of the key input elements.