公开(公告)号：US10977853B2

公开(公告)日：2021-04-13

申请号：US16791719

申请日：2020-02-14

Applicant: Intel Corporation

Inventor： Ingo Wald ,  Gabor Liktor ,  Carsten Benthin ,  Carson Brownlee ,  Johannes Guenther ,  Jefferson D. Amstutz

IPC: G06T15/00 ,  G06T9/00 ,  G06T15/06 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10

Abstract: An apparatus and method for compressing ray tracing data prior to transmission between nodes. For example, one embodiment of an apparatus comprises: a first node comprising a first ray tracing engine, the first node communicatively coupled to a second node comprising a second ray tracing engine; first compression circuitry coupled to the first ray tracing engine, the first compression circuitry to perform compression on ray tracing data of the first ray tracing engine to produce a first compressed stream of ray tracing data; and interface circuitry to transmit the first compressed stream of ray tracing data from the first node to the second node.

公开(公告)号：US10922790B2

公开(公告)日：2021-02-16

申请号：US16230501

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Carson Brownlee ,  Ingo Wald ,  Attila Afra ,  Johannes Guenther ,  Jefferson Amstutz ,  Carsten Benthin

IPC: G06T5/00 ,  G06T1/20 ,  G06T5/20 ,  G06T9/00 ,  G06T15/06

Abstract: Apparatus and method for denoising of images generated by a rendering engine such as a ray tracing engine. For example, one embodiment of a system or apparatus comprises: A system comprising: a plurality of nodes to perform ray tracing operations; a dispatcher node to dispatch graphics work to the plurality of nodes, each node to perform ray tracing to render a region of an image frame; at least a first node of the plurality comprising: a ray-tracing renderer to perform ray tracing to render a first region of the image frame; and a denoiser to perform denoising of the first region using a combination of data associated with the first region and data associated with a region outside of the first region, at least some of the data associated with the region outside of the first region to be retrieved from at least one other node.

公开(公告)号：US10755469B2

公开(公告)日：2020-08-25

申请号：US16235838

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Michael Apodaca ,  Thomas Raoux ,  Carsten Benthin ,  Kai Xiao ,  Carson Brownlee ,  Joshua Barczak

IPC: G06T15/06 ,  G06T1/60 ,  G06T9/00 ,  G06T5/00

Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.

公开(公告)号：US10740953B2

公开(公告)日：2020-08-11

申请号：US16235583

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Kai Xiao ,  Michael Apodaca ,  Carson Brownlee ,  Thomas Raoux ,  Joshua Barczak ,  Gabor Liktor

IPC: G06T15/06 ,  G06T1/20

Abstract: Apparatus and method for bottom-up BVH refit. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes; traversal hardware logic to traverse one or more rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure, the refit operations to adjust spatial dimensions of one or more of the nodes; and an early termination evaluator to determine whether to proceed with refit operations or to terminate refit operations for a current node based on refit data associated with one or more child nodes of the current node.

公开(公告)号：US20180284872A1

公开(公告)日：2018-10-04

申请号：US15477010

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Travis T. Schluessler ,  Joydeep Ray ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Kamal Sinha ,  James M. Holland ,  Pattabhiraman K. ,  Sayan Lahiri ,  Radhakrishnan Venkataraman ,  Carson Brownlee ,  Vivek Tiwari ,  Kai Xiao ,  Jefferson Amstutz ,  Deepak S. Vembar ,  Ankur N. Shah ,  ElMoustapha Ould-Ahmed-Vall

IPC: G06F1/32 ,  G06T1/20 ,  G06T7/13

Abstract: An embodiment may include an application processor, persistent storage media coupled to the application processor, and a graphics subsystem coupled to the application processor. The system may further include any of a performance analyzer to analyze a performance of the graphics subsystem to provide performance analysis information, a content-based depth analyzer to analyze content to provide content-based depth analysis information, a focus analyzer to analyze a focus area to provide focus analysis information, an edge analyzer to provide edge analysis information, a frame analyzer to provide frame analysis information, and/or a variance analyzer to analyze respective amounts of variance for the frame. The system may further include a workload adjuster to adjust a workload of the graphics subsystem based on the analysis information. Other embodiments are disclosed and claimed.