公开(公告)号：US20210249324A1

公开(公告)日：2021-08-12

申请号：US16783819

申请日：2020-02-06

Applicant: Intel Corporation

Inventor： Zhimin WAN ,  Chia-Pin CHIU ,  Chandra Mohan JHA

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises an interposer, a first die attached to the interposer, and a second die attached to the interposer. In an embodiment, the electronic package further comprises a heatsink thermally coupled to the first die and the second die. In an embodiment, the heatsink has a first surface facing away from the first die and the second die and a second surface facing the first die and the second die. In an embodiment, the heatsink comprises a thermal break between the first die and the second die.

公开(公告)号：US20210193548A1

公开(公告)日：2021-06-24

申请号：US16721807

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Zhimin WAN ,  Chia-Pin CHIU ,  Peng LI ,  Shankar DEVASENATHIPATHY

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/42 ,  H01L23/373 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48

Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first and second bottom dies on a package substrate. The semiconductor package includes first top dies on the first bottom die, second top dies on the second bottom die, and a pedestal on the first and second bottom dies. The pedestal comprises a high thermal conductive material and is positioned on a region of top surfaces of the first and second bottom dies. The semiconductor package includes an encapsulation layer over the first and second bottom dies, and surrounds the first and second top dies and the pedestal. The semiconductor package includes a TIM over the first and second top dies, pedestal, and encapsulation layer, and an integrated heat spreader (IHS) over the TIM. The pedestal is on a periphery region of the top surfaces of the first and second bottom dies.

公开(公告)号：US20210193547A1

公开(公告)日：2021-06-24

申请号：US16721802

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Zhimin WAN ,  Chandra Mohan JHA ,  Je-Young CHANG ,  Chia-Pin CHIU ,  Liwei WANG

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/42 ,  H01L23/373 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48

Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first, second, and third microelectronic devices on a package substrate. The first microelectronic device has a top surface substantially coplanar to a top surface of the second microelectronic device. The third microelectronic device has a top surface above the top surfaces of the first and second microelectronic devices. The semiconductor package includes a first conductive layer on the first and second microelectronic devices, and a second conductive layer on the third microelectronic device. The second conductive layer has a thickness less than a thickness of the first conductive layer, and a top surface substantially coplanar to a top surface of the first conductive layer. The semiconductor includes thermal interface materials on the first and second conductive layers. The first and second conductive layers are comprised of copper, silver, boron nitride, or graphene.

公开(公告)号：US20210043596A1

公开(公告)日：2021-02-11

申请号：US17077996

申请日：2020-10-22

Applicant: Intel Corporation

Inventor： Weng Hong TEH ,  Chia-Pin CHIU

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/16 ,  H01L23/50 ,  H01L25/18

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US20200075493A1

公开(公告)日：2020-03-05

申请号：US16677533

申请日：2019-11-07

Applicant: Intel Corporation

Inventor： Henning BRAUNISCH ,  Chia-Pin CHIU ,  Aleksandar ALEKSOV ,  Hinmeng AU ,  Stefanie M. LOTZ ,  Johanna M. SWAN ,  Sujit SHARAN

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/13

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

公开(公告)号：US20240429173A1

公开(公告)日：2024-12-26

申请号：US18823186

申请日：2024-09-03

Applicant: Intel Corporation

Inventor： Henning BRAUNISCH ,  Chia-Pin CHIU ,  Aleksandar ALEKSOV ,  Hinmeng AU ,  Stefanie M. LOTZ ,  Johanna M. SWAN ,  Sujit SHARAN

IPC: H01L23/538 ,  H01L21/683 ,  H01L23/00 ,  H01L23/13 ,  H01L25/065

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

公开(公告)号：US20240421073A1

公开(公告)日：2024-12-19

申请号：US18818285

申请日：2024-08-28

Applicant: Intel Corporation

Inventor： Robert STARKSTON ,  Debendra MALLIK ,  John S. GUZEK ,  Chia-Pin CHIU ,  Deepak KULKARNI ,  Ravi V. MAHAJAN

IPC: H01L23/522 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US20230040850A1

公开(公告)日：2023-02-09

申请号：US17972340

申请日：2022-10-24

Applicant: Intel Corporation

Inventor： Robert STARKSTON ,  Debendra MALLIK ,  John S. GUZEK ,  Chia-Pin CHIU ,  Deepak KULKARNI ,  Ravi V. MAHAJAN

IPC: H01L23/522 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US20220413236A1

公开(公告)日：2022-12-29

申请号：US17358502

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Omkar KARHADE ,  Sushrutha Reddy GUJJULA ,  Tolga ACIKALIN ,  Ravindranath V. MAHAJAN ,  James E. JAUSSI ,  Chia-Pin CHIU

IPC: G02B6/42 ,  H01L25/16 ,  H01L23/00 ,  H01L23/367 ,  H01S3/04

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to thermally and/or electrically coupling a thermal die to the surface of a photonic integrated circuit (PIC) within an open cavity in a substrate, where the thermal die is proximate to a laser on the PIC. Other embodiments may be described and/or claimed.

公开(公告)号：US20220196941A1

公开(公告)日：2022-06-23

申请号：US17125481

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Asako TODA ,  Chia-Pin CHIU ,  Xiaoqian LI ,  Yiqun BAI

IPC: G02B6/42

Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, where the package substrate comprises a recessed edge. In an embodiment, a compute die is on the package substrate, and an optics die on the package substrate and overhanging the recessed edge of the package substrate. In an embodiment, an integrated heat spreader (IHS) is over the compute die and the optics die. In an embodiment, a lid covers the recess in the package substrate