公开(公告)号：US20240429173A1

公开(公告)日：2024-12-26

申请号：US18823186

申请日：2024-09-03

Applicant: Intel Corporation

Inventor： Henning BRAUNISCH ,  Chia-Pin CHIU ,  Aleksandar ALEKSOV ,  Hinmeng AU ,  Stefanie M. LOTZ ,  Johanna M. SWAN ,  Sujit SHARAN

IPC: H01L23/538 ,  H01L21/683 ,  H01L23/00 ,  H01L23/13 ,  H01L25/065

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

公开(公告)号：US20220130743A1

公开(公告)日：2022-04-28

申请号：US17573479

申请日：2022-01-11

Applicant: Intel Corporation

Inventor： Arnab SARKAR ,  Sujit SHARAN ,  Dae-Woo KIM

IPC: H01L23/498 ,  H01L23/544 ,  H01L21/66 ,  H01L23/58 ,  H01L25/065 ,  H01L23/00

Abstract: Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure incudes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

公开(公告)号：US20210280518A1

公开(公告)日：2021-09-09

申请号：US16810192

申请日：2020-03-05

Applicant: Intel Corporation

Inventor： Jianyong XIE ,  Sujit SHARAN ,  Huang-Ta CHEN

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18 ,  H01L23/64

Abstract: Embodiments disclosed herein include electronic packages with a bridge that comprise improved power delivery architectures. In an embodiment, a bridge comprises a substrate and a routing stack over the substrate. In an embodiment, the routing stack comprises first routing layers, where individual ones of the first routing layers have a first thickness, and a second routing layer, where the second routing layer has a second thickness that is greater than the first thickness.

公开(公告)号：US20210134726A1

公开(公告)日：2021-05-06

申请号：US17144130

申请日：2021-01-07

Applicant: Intel Corporation

Inventor： Henning BRAUNISCH ,  Chia-Pin CHIU ,  Aleksandar ALEKSOV ,  Hinmeng AU ,  Stefanie M. LOTZ ,  Johanna M. SWAN ,  Sujit SHARAN

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/00 ,  H01L25/065

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

公开(公告)号：US20230343731A1

公开(公告)日：2023-10-26

申请号：US18214742

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Sujit SHARAN ,  Jianyong XIE

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/538 ,  H01L23/528 ,  H01L25/00 ,  H01L21/48 ,  H01L25/16

CPC classification number: H01L23/66 ,  H01L23/5223 ,  H01L23/5389 ,  H01L23/5286 ,  H01L25/50 ,  H01L21/4846 ,  H01L23/5381 ,  H01L25/16 ,  H01L23/481

Abstract: A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.

公开(公告)号：US20230260884A1

公开(公告)日：2023-08-17

申请号：US18138512

申请日：2023-04-24

Applicant: Intel Corporation

Inventor： Arnab SARKAR ,  Sujit SHARAN ,  Dae-Woo KIM

IPC: H01L23/498 ,  H01L23/544 ,  H01L21/66 ,  H01L23/58 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L23/544 ,  H01L22/32 ,  H01L23/585 ,  H01L25/0655 ,  H01L24/10 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/14 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/3512 ,  H01L24/16 ,  H01L25/18

Abstract: Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure incudes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

公开(公告)号：US20230238339A1

公开(公告)日：2023-07-27

申请号：US18128954

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Dae-Woo KIM ,  Sujit SHARAN ,  Sairam AGRAHARAM

IPC: H01L23/58 ,  H01L23/538

CPC classification number: H01L23/585 ,  H01L23/5385 ,  H01L23/544

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

公开(公告)号：US20200075493A1

公开(公告)日：2020-03-05

申请号：US16677533

申请日：2019-11-07

Applicant: Intel Corporation

Inventor： Henning BRAUNISCH ,  Chia-Pin CHIU ,  Aleksandar ALEKSOV ,  Hinmeng AU ,  Stefanie M. LOTZ ,  Johanna M. SWAN ,  Sujit SHARAN

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/13

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

公开(公告)号：US20190304935A1

公开(公告)日：2019-10-03

申请号：US15942092

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Sujit SHARAN ,  Jianyong XIE

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/538 ,  H01L23/528 ,  H01L25/00 ,  H01L25/16 ,  H01L21/48

Abstract: A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.

公开(公告)号：US20180226330A1

公开(公告)日：2018-08-09

申请号：US15749462

申请日：2015-10-29

Applicant: Intel Corporation

Inventor： Dae-Woo KIM ,  Sujit SHARAN

IPC: H01L23/498 ,  H01L23/13 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L23/13 ,  H01L23/48 ,  H01L23/49822 ,  H01L24/00 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2924/1431 ,  H01L2924/1435 ,  H01L2924/1517 ,  H01L2924/153

Abstract: Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.