公开(公告)号：US20230317621A1

公开(公告)日：2023-10-05

申请号：US17707708

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Bernd WAIDHAS ,  David O'SULLIVAN ,  Georg SEIDEMANN

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/5384 ,  H01L24/08 ,  H01L23/5383 ,  H01L23/15 ,  H01L25/0655 ,  H01L24/05 ,  H01L24/80 ,  H01L23/49811 ,  H01L21/486 ,  H01L2224/08225 ,  H01L2224/05647 ,  H01L2224/80447 ,  H01L2224/80895

Abstract: Embodiments herein relate to systems, apparatuses, techniques, or processes directed to semiconductor packages that include a glass interposer that includes electrically conductive through glass vias that extend through the interposer. One or more dies may be hybrid bonded to a first side of the glass interposer. In embodiments, the second side of the glass interposer may include a redistribution layer that is electrically coupled with the one or more dies through the through glass vias. Other embodiments may be described and/or claimed.

公开(公告)号：US20230102133A1

公开(公告)日：2023-03-30

申请号：US17448734

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Martin OSTERMAYR ,  Walther LUTZ ,  Joachim ASSENMACHER ,  Georg SEIDEMANN

IPC: H01L23/64 ,  H01L23/00

Abstract: A semiconductor die is disclosed, including circuitry comprising a transistor at a frontside of a semiconductor substrate, and a backside inductor at a backside of the semiconductor substrate. The backside inductor is electrically connected to the transistor of the circuitry.

公开(公告)号：US20220199562A1

公开(公告)日：2022-06-23

申请号：US17131663

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Bernd WAIDHAS ,  Andreas WOLTER ,  Georg SEIDEMANN ,  Thomas WAGNER

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic package and methods of forming such packages. In an embodiment, an electronic package comprises a mold layer and a first die embedded in the mold layer. In an embodiment, the first die comprises first pads at a first pitch and second pads at a second pitch. In an embodiment, the electronic package further comprises a second die embedded in the mold layer, where the second die comprises third pads at the first pitch and fourth pads at the second pitch. In an embodiment, a bridge die is embedded in the mold layer, and the bridge die electrically couples the second pads to the fourth pads.

公开(公告)号：US20220108976A1

公开(公告)日：2022-04-07

申请号：US17553679

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Georg SEIDEMANN ,  Klaus REINGRUBER ,  Christian GEISSLER ,  Sven ALBERS ,  Andreas WOLTER ,  Marc DITTES ,  Richard PATTEN

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.