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    Semiconductor Devices and Methods for Forming a Semiconductor Device
    3.
    发明申请
    Semiconductor Devices and Methods for Forming a Semiconductor Device 有权

    公开(公告)号：US20230095162A1

    公开(公告)日：2023-03-30

    申请号：US17448714

    申请日：2021-09-24

    Applicant: Intel Corporation

    Inventor： Georg SEIDEMANN ,  Martin OSTERMAYR ,  Walther LUTZ ,  Joachim ASSENMACHER

    IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/495 ,  H01L23/31 ,  H01L25/065

    Abstract: A semiconductor device is provided. The semiconductor device comprises a semiconductor die comprising a semiconductor substrate and a plurality of transistors arranged at a front side of the semiconductor substrate. Further, the semiconductor die comprises a first electrically conductive structure extending from the front side of the semiconductor substrate to a backside of the semiconductor substrate and a second electrically conductive structure extending from the front side of the semiconductor substrate to the backside of the semiconductor substrate. The semiconductor device further comprises an interposer directly attached to the backside of the semiconductor substrate. The interposer comprises a first trace electrically connected to the first electrically conductive structure of the semiconductor die. Further the interposer comprises the first trace or a second trace electrically connected to the second electrically conductive structure of the semiconductor die.

    NOVEL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP), FLIP-CHIP CHIP SCALE PACKAGE (FCCSP), AND FAN OUT SHIELDING CONCEPTS
    4.
    发明申请
    NOVEL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP), FLIP-CHIP CHIP SCALE PACKAGE (FCCSP), AND FAN OUT SHIELDING CONCEPTS 审中-公开

    公开(公告)号：US20200098698A1

    公开(公告)日：2020-03-26

    申请号：US16143212

    申请日：2018-09-26

    Applicant: Intel Corporation

    Inventor： Richard PATTEN ,  David O'SULLIVAN ,  Georg SEIDEMANN ,  Bernd WAIDHAS

    IPC: H01L23/552 ,  H01L23/31 ,  H01L23/522

    Abstract: Embodiments include semiconductor packages, such as wafer level chip scale packages (WLCSPs), flip chip chip scale packages (FCCSPs), and fan out packages. The WLCSP includes a first doped region on a second doped region, a dielectric on a redistribution layer, where the dielectric is between the redistribution layer and doped regions. The WLCSP also includes a shield over the doped regions, the dielectric, and the redistribution layer, where the shield includes a plurality of surfaces, and at least one of the plurality of surfaces of the shield is on a top surface of the first doped region. The WLCSP may have interconnects coupled to the second doped region and redistribution layer. The shield may be a conductive shield that is coupled to ground, and the shield may be directly coupled to the redistribution layer and first doped region. The first and second doped regions may include highly doped n-type materials.

    GROOVED PACKAGE
    7.
    发明公开
    GROOVED PACKAGE 审中-公开

    公开(公告)号：US20230317536A1

    公开(公告)日：2023-10-05

    申请号：US17707536

    申请日：2022-03-29

    Applicant: Intel Corporation

    Inventor： Georg SEIDEMANN ,  Bernd WAIDHAS ,  Thomas WAGNER ,  Stephan STOECKL

    IPC: H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L21/56

    CPC classification number: H01L23/3107 ,  H01L23/5381 ,  H01L25/0655 ,  H01L21/56

    Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes related to packages that are fully or partially encapsulated in a mold material, with one or more grooves in the mold material to reduce failure in the package during operation. In embodiments, the grooves will allow greater flexibility within the body of the package as it experiences thermo-mechanical stress during operation and will reduce stresses that may be placed on internal components such as chips or bridges in the package, as well as stresses that may be placed on interconnects of the package that are coupled to a substrate. Other embodiments may be described and/or claimed.

    STRESS RELIEF DIE IMPLEMENTATION
    9.
    发明申请
    STRESS RELIEF DIE IMPLEMENTATION 有权

    公开(公告)号：US20210193594A1

    公开(公告)日：2021-06-24

    申请号：US16721095

    申请日：2019-12-19

    Applicant: Intel Corporation

    Inventor： Stephan STOECKL ,  Wolfgang MOLZER ,  Georg SEIDEMANN ,  Bernd WAIDHAS

    IPC: H01L23/58 ,  H01L23/31 ,  H01L49/02 ,  H01L21/683 ,  H01L21/56

    Abstract: Embodiments disclosed herein include semiconductor packages. In a particular embodiment, the semiconductor package is a wafer level chip scale package (WLCSP). In an embodiment, the WLCSP comprises a die. In an embodiment, the die comprises an active surface and a backside surface. The die has a first coefficient of thermal expansion (CTE). In an embodiment, the WLCSP further comprises a channel into the die. In an embodiment, the channel is filled with a stress relief material, where the stress relief material has a second CTE that is greater than the first CTE.

    METHOD TO IMPLEMENT WAFER-LEVEL CHIP-SCALE PACKAGES WITH GROUNDED CONFORMAL SHIELD
    10.
    发明申请
    METHOD TO IMPLEMENT WAFER-LEVEL CHIP-SCALE PACKAGES WITH GROUNDED CONFORMAL SHIELD 审中-公开

    公开(公告)号：US20200312781A1

    公开(公告)日：2020-10-01

    申请号：US16368032

    申请日：2019-03-28

    Applicant: Intel Corporation

    Inventor： Gianni SIGNORINI ,  Georg SEIDEMANN ,  Bernd WAIDHAS

    IPC: H01L23/552 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/78

    Abstract: Embodiments disclosed herein include electronic packages with conformal shields and methods of forming such packages. In an embodiment, the electronic package comprises a die having a first surface, a second surface opposite the first surface, and sidewall surfaces. A redistribution layer is over the first surface of the die, and the redistribution layer comprises a first conductive layer. In an embodiment, an under ball metallization (UBM) layer is over the redistribution layer, and a conductive shield is over the sidewall surfaces of the die and the second surface of the die. In an embodiment, the conductive shield is electrically coupled to the UBM layer.

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