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21.发明申请公开(公告)号：US20200334896A1
公开(公告)日：2020-10-22
申请号：US16865587
申请日：2020-05-04
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Karthik Vaidyanathan , Atsuo Kuwahara , Hugues Labbe , Sameer Kp , Jonathan Kennedy , Abhishek R. Appu , Jeffery S. Boles , Balaji Vembu , Michael Apodaca , Slawomir Grajewski , Gabor Liktor , David M. Cimini , Andrew T. Lauritzen , Travis T. Schluessler , Murali Ramadoss , Abhishek Venkatesh , Joydeep Ray , Kai Xiao , Ankur N. Shah , Altug Koker
Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones.
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公开(公告)号：US20200045348A1
公开(公告)日：2020-02-06
申请号：US16050475
申请日：2018-07-31
Applicant: Intel Corporation
Inventor： Jill Boyce , Scott Janus , Prasoonkumar Surti , Stanley Baran , Michael Apodaca , Srikanth Potluri , Hugues Labbe , Jong Dae Oh , Gokcen Cilingir , Archie Sharma , Jeffrey Tripp , Jason Ross , Barnan Das
IPC: H04N21/235 , H04N21/435 , H04N21/845 , H04N21/2662 , G06T15/00 , G06T15/80 , G06T15/50
Abstract: An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to decode point cloud data, reconstruct the decoded point cloud data and fill one or more holes in reconstructed point cloud frame data using patch metadata included in the decoded point cloud data and a memory communicatively coupled to the one or more processors.
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公开(公告)号：US20200045343A1
公开(公告)日：2020-02-06
申请号：US16050391
申请日：2018-07-31
Applicant: Intel Corporation
Inventor： Jill Boyce , Scott Janus , Itay Kaufman , Archie Sharma , Stanley Baran , Michael Apodaca , Prasoonkumar Surti , Srikanth Potluri , Barnan Das , Hugues Labbe , Jong Dae Oh , Gokcen Cilingir , Maria Bortman , Tzach Ashkenazi , Jonathan Distler , Atul Divekar , Mayuresh M. Varerkar , Narayan Biswal , Nilesh V. Shah , Atsuo Kuwahara , Kai Xiao , Jason Tanner , Jeffrey Tripp
Abstract: An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to encode surface normals data with point cloud geometry data included in the video bit stream data for reconstruction of objects within the video bit stream data based on the surface normals data and a memory communicatively coupled to the one or more processors.
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公开(公告)号：US20200035005A1
公开(公告)日：2020-01-30
申请号：US16533920
申请日：2019-08-07
Applicant: Intel Corporation
Inventor： Deepak S. Vembar , Atsuo Kuwahara , Chandrasekaran Sakthivel , Radhakrishnan Venkataraman , Brent E. Insko , Anupreet S. Kalra , Hugues Labbe , Abhishek R. Appu , Ankur N. Shah , Joydeep Ray , ElMoustapha Ould-Ahmed-Vall , James M. Holland
IPC: G06T11/60 , H04N19/124 , H04N19/167 , H04N19/17 , H04N19/436 , H04N19/503 , G06T9/00
Abstract: An embodiment of a graphics apparatus may include a focus identifier to identify a focus area, and a color compressor to selectively compress color data based on the identified focus area. Another embodiment of a graphics apparatus may include a motion detector to detect motion of a real object, a motion predictor to predict a motion of the real object, and an object placer to place a virtual object relative to the real object based on the predicted motion of the real object. Another embodiment of a graphics apparatus may include a frame divider to divide a frame into viewports, a viewport prioritizer to prioritize the viewports, a renderer to render a viewport of the frame in order in accordance with the viewport priorities, and a viewport transmitter to transmit a completed rendered viewport. Other embodiments are disclosed and claimed.
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25.发明授权公开(公告)号：US10452552B2
公开(公告)日：2019-10-22
申请号：US15488988
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Andrew T. Lauritzen , Gabor Liktor , Tomer Bar-On , Hugues Labbe , John G. Gierach , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Abhishek R. Appu , Balaji Vembu , Altug Koker
IPC: G06F12/0862 , G06F9/30 , G06F12/0875 , G06F12/0811 , G06F12/0855 , G06F9/38 , G06T1/20
Abstract: Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.
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Patent Agency Ranking
公开(公告)号：US20190147640A1
公开(公告)日：2019-05-16
申请号：US16173722
申请日：2018-10-29
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Karthik Vaidyanathan , Atsuo Kuwahara , Hugues Labbe , Sameer KP , Jonathan Kennedy , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Tomer Bar-On , Carsten Benthin , Adam T. Lake , Vasanth Ranganathan , Abhishek R. Appu
IPC: G06T15/08 , H04N5/369 , G06T15/00 , G06T15/60 , G06T15/10 , H04N5/232 , H04N13/239 , H04N13/344 , G06K9/00 , G02B27/01
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.
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27.发明申请公开(公告)号：US20180293961A1
公开(公告)日：2018-10-11
申请号：US15483748
申请日：2017-04-10
Applicant: Intel Corporation
Inventor： Hugues Labbe , Karthik Vaidyanathan , Prasoonkumar Surti , Atsuo Kuwahara , Sameer Kp , Jonathan Kennedy
Abstract: Systems and methods may provide for determining a start time for an output image scanner to begin scanning an output image to a display device, determining a processing start time for each row of blocks of image pixel data within a rasterizer to ensure its completion before each row of blocks of image pixel data within the output image begin to be scanned out, and scheduling the start of processing of each row of blocks of image pixel data. In one example, the start time for the rasterizer to process a row of blocks of image pixel data uses the number of graphical objects to rendered into the output image and the processing times required by prior images.
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公开(公告)号：US12271991B2
公开(公告)日：2025-04-08
申请号：US18324611
申请日：2023-05-26
Applicant: Intel Corporation
Inventor： Hugues Labbe , Tomer Bar-On , Gabor Liktor , Andrew T. Lauritzen , John G. Gierach
Abstract: Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.
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公开(公告)号：US12243125B2
公开(公告)日：2025-03-04
申请号：US18517318
申请日：2023-11-22
Applicant: Intel Corporation
Inventor： Karthik Vaidyanathan , Prasoonkumar Surti , Hugues Labbe , Atsuo Kuwahara , Sameer KP , Jonathan Kennedy , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh
Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
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公开(公告)号：US11869119B2
公开(公告)日：2024-01-09
申请号：US17666193
申请日：2022-02-07
Applicant: Intel Corporation
Inventor： Karthik Vaidyanathan , Prasoonkumar Surti , Hugues Labbe , Atsuo Kuwahara , Sameer Kp , Jonathan Kennedy , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh
CPC classification number: G06T11/001 , G06T1/20 , G06T1/60 , G06T15/005 , G06T2210/52
Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
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