公开(公告)号：US10671457B2

公开(公告)日：2020-06-02

申请号：US14670733

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Mario Flajslik ,  James Dinan

IPC: G06F9/54 ,  G06F9/52

Abstract: Systems, apparatuses and methods may provide for detecting an outbound communication and identifying a context of the outbound communication. Additionally, a completion status of the outbound communication may be tracked relative to the context. In one example, tracking the completion status includes incrementing a sent messages counter associated with the context in response to the outbound communication, detecting an acknowledgement of the outbound communication based on a network response to the outbound communication, incrementing a received acknowledgements counter associated with the context in response to the acknowledgement, comparing the sent messages counter to the received acknowledgements counter, and triggering a per-context memory ordering operation if the sent messages counter and the received acknowledgements counter have matching values.

公开(公告)号：US10652353B2

公开(公告)日：2020-05-12

申请号：US14864369

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： James Dinan ,  Venkata Krishnan ,  Srinivas Sridharan ,  David A. Webb

IPC: G06F15/16 ,  H04L29/08 ,  G06F15/173

Abstract: Technologies for communication with direct data placement include a number of computing nodes in communication over a network. Each computing node includes a many-core processor having an integrated host fabric interface (HFI) that maintains an association table (AT). In response to receiving a message from a remote device, the HFI determines whether the AT includes an entry associating one or more parameters of the message to a destination processor core. If so, the HFI causes a data transfer agent (DTA) of the destination core to receive the message data. The DTA may place the message data in a private cache of the destination core. Message parameters may include a destination process identifier or other network address and a virtual memory address range. The HFI may automatically update the AT based on communication operations generated by software executed by the processor cores. Other embodiments are described and claimed.

公开(公告)号：US10574733B2

公开(公告)日：2020-02-25

申请号：US14858051

申请日：2015-09-18

Applicant: Intel Corporation

Inventor： James Dinan ,  Mario Flajslik ,  Keith D. Underwood

IPC: H04L29/08 ,  H04L12/863 ,  H04L12/743

Abstract: Technologies for handling message passing interface receive operations include a compute node to determine a plurality of parameters of a receive entry to be posted and determine whether the plurality of parameters includes a wildcard entry. The compute node generates a hash based on at least one parameter of the plurality of parameters in response to determining that the plurality of parameters does not include the wildcard entry and appends the receive entry to a list in a bin of a posted receive data structure, wherein the bin is determined based on the generated hash. The compute node further tracks the wildcard entry in the posted receive data structure in response to determining the plurality of parameters includes the wildcard entry and appends the receive entry to a wildcard list of the posted receive data structure in response to tracking the wildcard entry.

公开(公告)号：US10554568B2

公开(公告)日：2020-02-04

申请号：US14866559

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Mario Flajslik ,  James Dinan

IPC: H04L12/841 ,  H04L12/26

Abstract: Technologies for estimating network round-trip times include a sender computing node in network communication with a set of neighboring computing nodes. The sender computing node is configured to determine the set of neighboring computing nodes, as well as a plurality of subsets of the set of neighboring computing nodes. Accordingly, the sender computing node generates a message queue for each of the plurality of subsets, each message queue including a probe message for each neighboring node in the subset to which the message queue corresponds. The sender computing node is further configured to determine a round-trip time for each message queue (i.e., subset of neighboring computing nodes) based on a duration of time between the first probe message of the message queue being transmitted and an acknowledgment being received in response to the last probe message of the message queue being transmitted. Additionally, the sender computing node is configured to estimate a round-trip time for each of the neighboring computing nodes based on the round-trip times determined for each message queue. Other embodiments are described and claimed.

公开(公告)号：US10178041B2

公开(公告)日：2019-01-08

申请号：US14862854

申请日：2015-09-23

Applicant: Intel Corporation

Inventor： James Dinan ,  Mario Flajslik ,  David Keppel ,  Ulf R. Hanebutte

IPC: H04L12/26 ,  H04L12/863 ,  H04L12/801 ,  H04L12/891 ,  H04L12/835

Abstract: Technologies for aggregation-based message processing include multiple computing nodes in communication over a network. A computing node receives a message from a remote computing node, increments an event counter in response to receiving the message, determines whether an event trigger is satisfied in response to incrementing the counter, and writes a completion event to an event queue if the event trigger is satisfied. An application of the computing node monitors the event queue for the completion event. The application may be executed by a processor core of the computing node, and the other operations may be performed by a host fabric interface of the computing node. The computing node may be a target node and count one-sided messages received from an initiator node, or the computing node may be an initiator node and count acknowledgement messages received from a target node. Other embodiments are described and claimed.

公开(公告)号：US10073809B2

公开(公告)日：2018-09-11

申请号：US14696719

申请日：2015-04-27

Applicant: Intel Corporation

Inventor： James Dinan ,  Mario Flajslik

IPC: G06F3/06 ,  G06F15/173

CPC classification number: G06F15/17331 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/067

Abstract: Technologies for one-side remote memory access communication include multiple computing nodes in communication over a network. A receiver computing node receives a message from a sender node and extracts a segment identifier from the message. The receiver computing node determines, based on the segment identifier, a segment start address associated with a partitioned global address space (PGAS) segment of its local memory. The receiver computing node may index a segment table stored in the local memory or in a host fabric interface. The receiver computing node determines a local destination address within the PGAS segment based on the segment start address and an offset included in the message. The receiver computing node performs a remote memory access operation at the local destination address. The receiver computing node may perform those operations in hardware by the host fabric interface of the receiver computing node. Other embodiments are described and claimed.

公开(公告)号：US20170085442A1

公开(公告)日：2017-03-23

申请号：US14862854

申请日：2015-09-23

Applicant: Intel Corporation

Inventor： James Dinan ,  Mario Flajslik ,  David Keppel ,  Ulf R. Hanebutte

IPC: H04L12/26 ,  H04L12/863

CPC classification number: H04L47/62 ,  H04L43/04 ,  H04L43/16 ,  H04L47/10 ,  H04L47/30 ,  H04L47/41 ,  Y02D50/30

Abstract: Technologies for aggregation-based message processing include multiple computing nodes in communication over a network. A computing node receives a message from a remote computing node, increments an event counter in response to receiving the message, determines whether an event trigger is satisfied in response to incrementing the counter, and writes a completion event to an event queue if the event trigger is satisfied. An application of the computing node monitors the event queue for the completion event. The application may be executed by a processor core of the computing node, and the other operations may be performed by a host fabric interface of the computing node. The computing node may be a target node and count one-sided messages received from an initiator node, or the computing node may be an initiator node and count acknowledgement messages received from a target node. Other embodiments are described and claimed.

公开(公告)号：US20160283295A1

公开(公告)日：2016-09-29

申请号：US14670733

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Mario Flajslik ,  James Dinan

IPC: G06F9/54 ,  G06F9/46

Abstract: Systems, apparatuses and methods may provide for detecting an outbound communication and identifying a context of the outbound communication. Additionally, a completion status of the outbound communication may be tracked relative to the context. In one example, tracking the completion status includes incrementing a sent messages counter associated with the context in response to the outbound communication, detecting an acknowledgement of the outbound communication based on a network response to the outbound communication, incrementing a received acknowledgements counter associated with the context in response to the acknowledgement, comparing the sent messages counter to the received acknowledgements counter, and triggering a per-context memory ordering operation if the sent messages counter and the received acknowledgements counter have matching values.

Abstract translation: 系统，装置和方法可以提供检测出站通信和识别出站通信的上下文。 此外，可以相对于上下文跟踪出站通信的完成状态。 在一个示例中，跟踪完成状态包括响应于出站通信增加与上下文相关联的发送消息计数器，基于对出站通信的网络响应来检测出站通信的确认，递增与所接收到的确认计数器相关联的确认 响应于确认，将所发送的消息计数器与接收到的确认计数器进行比较，并且如果所发送的消息计数器和接收的确认计数器具有匹配值，则触发每上下文存储器排序操作。

公开(公告)号：US20160100010A1

公开(公告)日：2016-04-07

申请号：US14582240

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Mario Flajslik ,  James Dinan

IPC: H04L29/08 ,  G06F12/06

CPC classification number: H04L67/1097 ,  G06F12/0653 ,  G06F12/0692 ,  G06F2212/154

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for improved coordination between sender and receiver nodes in a one-sided memory access to a PGAS in a distributed computing environment. The system may include a transceiver module configured to receive a message over a network, the message comprising a data portion and a data size indicator and an offset handler module configured to calculate a destination address from a base address of a memory buffer and an offset counter. The transceiver module may further be configured to write the data portion to the memory buffer at the destination address; and the offset handler module may further be configured to update the offset counter based on the data size indicator.

Abstract translation: 通常，本公开提供了系统，设备，方法和计算机可读介质，用于改进在分布式计算环境中单向存储器访问PGAS的发送器和接收器节点之间的协调。 所述系统可以包括被配置为通过网络接收消息的收发器模块，所述消息包括数据部分和数据大小指示符，以及偏移处理器模块，被配置为从存储器缓冲器的基址和偏移计数器计算目的地地址 。 收发器模块还可以被配置为将数据部分写入目的地址处的存储器缓冲器; 并且偏移处理器模块还可以被配置为基于数据大小指示符来更新偏移计数器。

公开(公告)号：US11645534B2

公开(公告)日：2023-05-09

申请号：US16127416

申请日：2018-09-11

Applicant: Intel Corporation

Inventor： Sayantan Sur ,  James Dinan ,  Maria Garzaran ,  Anupama Kurpad ,  Andrew Friedley ,  Nusrat Islam ,  Robert Zak

IPC: G06N3/08 ,  G06N3/063 ,  G06N3/04 ,  G06N3/084

CPC classification number: G06N3/084 ,  G06N3/04 ,  G06N3/063

Abstract: An embodiment of a semiconductor package apparatus may include technology to embed one or more trigger operations in one or more messages related to collective operations for a neural network, and issue the one or more messages related to the collective operations to a hardware-based message scheduler in a desired order of execution. Other embodiments are disclosed and claimed.