-
公开(公告)号:US11354564B2
公开(公告)日:2022-06-07
申请号:US16454318
申请日:2019-06-27
Applicant: Intel Corporation
Inventor: Alexander Heinecke , Evangelos Georganas , Justin Gottschlich
Abstract: An example includes a sequence generator to generate a plurality of sequence pairs, a first one of the sequence pairs including: (i) a first input sequence representing first accesses to first tensors in a first loop nest of a first computer program, and (ii) a first output sequence representing a first tuned loop nest corresponding to the first accesses to the first tensors in the first loop nest; a model trainer to train a recurrent neural network based on the sequence pairs as training data, the recurrent neural network to be trained to tune loop ordering of a second computer program based on a second input sequence representing second accesses to a second tensor in a second loop nest of the second computer program; and a memory interface to store, in memory, a trained model corresponding to the recurrent neural network.
-
公开(公告)号:US20220171626A1
公开(公告)日:2022-06-02
申请号:US17672142
申请日:2022-02-15
Applicant: Intel Corporation
Inventor: Adam Herr , Derek Gerstmann , Justin Gottschlich , Mikael Bourges-Sevenier , Sridhar Sharma
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for intentional programming for heterogeneous systems. An example non-transitory computer readable storage medium includes instructions that, when executed, cause processor circuitry to at least identify a first code block having a first algorithmic purpose based on a second code block having a second algorithmic purpose, the second algorithmic purpose corresponding to the first algorithmic purpose, translate the first code block into executable domain specific language code, and output the executable domain specific language code.
-
23.
公开(公告)号:US11340874B2
公开(公告)日:2022-05-24
申请号:US16455259
申请日:2019-06-27
Applicant: Intel Corporation
Inventor: Thijs Metsch , Mohammad Mejbah Ul Alam , Justin Gottschlich
Abstract: Methods, apparatus, systems and articles of manufacture to recommend instruction adaptations to improve compute performance are disclosed. An example apparatus includes a pattern detector to detect an execution pattern from an execution profile provided by a server, the execution profile associated with an instruction stored in an instruction repository. An adaptation identifier is to identify a possible instruction adaptation that may be applied to the instruction associated with the execution pattern. A model processor is to predict, using a machine learning model, an expected performance improvement of the adaptation. A result comparator is to determine whether the expected performance improvement meets an threshold. An instruction editor is to, in response to the result comparator determining that the expected performance improvement meets the threshold, apply the possible instruction adaptation to the instruction in the instruction repository.
-
公开(公告)号:US20220124503A1
公开(公告)日:2022-04-21
申请号:US17545721
申请日:2021-12-08
Applicant: INTEL CORPORATION
Inventor: Liuyang Lily Yang , Debabani Choudhury , Sridhar Sharma , Kathiravetpillai Sivanesan , Justin Gottschlich , Zheng Zhang , Yair Yona , Xiruo Liu , Moreno Ambrosin , Kuilin Clark Chen
IPC: H04W12/12 , H04W4/40 , H04W12/06 , H04L9/32 , H04W12/122
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to detect attacks in V2X networks. An example apparatus includes a challenge handler to (a) transmit a first challenge packet to a first vehicle to request a transmission of a first response, (b) instruct a second challenge packet to be transmitted to a second vehicle to request a transmission of a second response, (c) increment a first counter when the first response is not obtained, (d) increment a second counter when the second response is not obtained, and (e) after repeating (a)-(d), determine that the first and second vehicles are phantom vehicles associated with an attacker with a half-duplex radio when at least one of the first or second counters satisfy a threshold, and a network interface to instruct a third vehicle associated with the V2X network to ignore future messages from the phantom vehicles based on the determination.
-
公开(公告)号:US20220091895A1
公开(公告)日:2022-03-24
申请号:US17541016
申请日:2021-12-02
Applicant: Intel Corporation
Inventor: Niranjan Hasabnis , Justin Gottschlich , Jesmin Jahan Tithi , Anand Venkat
Abstract: Methods, apparatus, systems, and articles of manufacture to determine execution cost are disclosed. An example apparatus includes memory; instructions included in the apparatus; and processor circuitry to execute the instruction to: cause a plurality of instructions corresponding to a mnemonic to be executed; determine an average execution cost of the plurality of instructions; determine a standard deviation of execution costs of the plurality of instructions; and generate a mapping table including an entry, the entry including the mnemonic in association with the average and the standard deviation.
-
公开(公告)号:US11269639B2
公开(公告)日:2022-03-08
申请号:US16455388
申请日:2019-06-27
Applicant: Intel Corporation
Inventor: Adam Herr , Derek Gerstmann , Justin Gottschlich , Mikael Bourges-Sevenier , Sridhar Sharma
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for intentional programming for heterogeneous systems. An example apparatus includes a code lifter to identify annotated code corresponding to an algorithm to be executed on the heterogeneous system based on an identifier being associated with the annotated code, and convert the annotated code in the first representation to intermediate code in a second representation by identifying the intermediate code as having a first algorithmic intent that corresponds to a second algorithmic intent of the annotated code, a domain specific language (DSL) generator to translate the intermediate code in the second representation to DSL code in a third representation when the first algorithmic intent matches the second algorithmic intent, the third representation corresponding to a DSL representation, and a code replacer to invoke a compiler to generate an executable including variant binaries based on the DSL code.
-
公开(公告)号:US11269622B2
公开(公告)日:2022-03-08
申请号:US16457006
申请日:2019-06-28
Applicant: Intel Corporation
Inventor: Mohammad Mejbah Ul Alam , David I. Gonzalez Aguirre , Shengtian Zhou , Justin Gottschlich , Li Chen
IPC: G06F8/71 , G06F8/75 , G06F8/77 , G06F17/11 , G06F40/40 , G06F16/906 , G06F16/9035 , G06N3/04
Abstract: Apparatus, systems, articles of manufacture, and methods for a context and complexity-aware recommendation system for efficient software development. An example apparatus includes a current state generator to generate a representation of a current state of a new function, an instruction predictor to generate a first recommended software component based on the current state of the new function, a complexity cost determiner to rank the first recommended software component based on a weighted sum of associated partial cost values, the software component to be ranked against second recommended software components based on a comparison of partial cost values corresponding to respective ones of the second recommended software components, a risk identifier to detect vulnerabilities based on an attack surface of a portion of the first recommended software component, and a ranking determiner to generate a third recommended software component, the third recommended software component corresponding to respective ranking metrics.
-
公开(公告)号:US11213947B2
公开(公告)日:2022-01-04
申请号:US16455263
申请日:2019-06-27
Applicant: Intel Corporation
Inventor: Javier Felip Leon , David Israel Gonzalez Aguirre , Javier Sebastián Turek , Ignacio Javier Alvarez , Luis Carlos Maria Remis , Justin Gottschlich
IPC: B25J9/16
Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for object manipulation via action sequence optimization. An example method disclosed herein includes determining an initial state of a scene, generating a first action phase sequence to transform the initial state of the scene to a solution state of the scene by selecting a plurality of action phases based on action phase probabilities, determining whether a first simulated outcome of executing the first action phase sequence satisfies an acceptability criterion and, when the first simulated outcome does not satisfy the acceptability criterion, calculating a first cost function output based on a difference between the first simulated outcome and the solution state of the scene, the first cost function output utilized to generate updated action phase probabilities.
-
公开(公告)号:US20210182031A1
公开(公告)日:2021-06-17
申请号:US17133238
申请日:2020-12-23
Applicant: Intel Corporation
Inventor: Fangke Ye , Justin Gottschlich , Shengtian Zhou , Roshni Iyer , Jesmin Jahan Tithi
Abstract: Methods, systems, and apparatus for automatic detection of software bugs are disclosed. An example apparatus includes a comparator to compare reference code to input code to detect a source code error in the input code; a graph generator to generate a graphical representation of the reference code or the input code, the graphical representation to identify non-overlapping code regions; and a root cause determiner to determine a root cause of the source code error in the input code, the root cause based on the non-overlapping code regions.
-
公开(公告)号:US20210157968A1
公开(公告)日:2021-05-27
申请号:US17107444
申请日:2020-11-30
Applicant: Intel Corporation
Inventor: Javier Sebastián Turek , Javier Felip Leon , Alexander Heinecke , Evangelos Georganas , Luis Carlos Maria Remis , Ignacio Javier Alvarez , David Israel Gonzalez Aguirre , Shengtian Zhou , Justin Gottschlich
IPC: G06F30/398 , G06N3/04 , G06N3/08
Abstract: Systems and methods for determining a configuration for a microarchitecture are described herein. An example system includes a proposal generator to generate a first candidate configuration of parameters for the microarchitecture, a machine learning model to process the first candidate configuration of parameters to output estimated performance indicators for the microarchitecture, an uncertainty checker to determine whether the estimated performance indicators are reliable, and a performance checker. In response to a determination that the estimated performance indicators are reliable, the performance checker is to determine whether the estimated performance indicators have improved toward a target. Further, if the estimated performance indicators have improved, the performance checker is to store the first candidate configuration of parameters in a memory as a potential solution for a microarchitecture without performing a full simulation on the first candidate configuration of parameters.
-
-
-
-
-
-
-
-
-