公开(公告)号：US08924620B2

公开(公告)日：2014-12-30

申请号：US14011009

申请日：2013-08-27

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Mahesh Wagh ,  Robert E. Gough ,  James E. Jaussi

IPC: G06F13/20 ,  G06F13/40

CPC classification number: G06F13/4027 ,  G06F1/3203 ,  G06F13/20 ,  G06F13/4295 ,  G06N99/005 ,  Y02D10/14 ,  Y02D10/151

Abstract: In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有事务层和链路层的协议栈。 另外，第一物理（PHY）单元被耦合到协议栈，以经由物理链路提供处理器和耦合到处理器的设备之间的通信，其中第一PHY单元是低功率通信协议，并且包括第一物理 单位电路。 反过来，第二PHY单元被耦合到协议栈，以经由耦合在与物理链路分离的多核处理器和设备之间的边带信道来提供处理器和设备之间的通信，其中第二PHY单元包括第二物理单元 电路。 描述和要求保护其他实施例。

公开(公告)号：US08745303B2

公开(公告)日：2014-06-03

申请号：US13891501

申请日：2013-05-10

Applicant: Intel Corporation

Inventor： Arvind Mandhani ,  Woojong Han ,  Ken Shoemaker ,  Madhu Athreya ,  Mahesh Wagh ,  Shreekant S. Thakkar

IPC: G06F13/42 ,  G06F13/20 ,  G06F13/40 ,  G06F13/36

CPC classification number: G06F13/4022 ,  G06F13/4027 ,  G06F13/404 ,  G06F13/4045 ,  G06F13/42

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有根据个人计算机（PC）协议和第二协议进行通信的适配器的装置。 耦合到适配器的第一接口是对从适配器的上游接收的事务执行地址转换和排序。 第一个接口依次耦合到异构资源，每个资源包括知识产权（IP）核心和垫片，其中垫片将为IP核实现PC协议的头部，以使其能够并入设备中而无需 修改。 描述和要求保护其他实施例。

公开(公告)号：US12222881B2

公开(公告)日：2025-02-11

申请号：US17231152

申请日：2021-04-15

Applicant: Intel Corporation

Inventor： Swadesh Choudhary ,  Mahesh Wagh ,  Debendra Das Sharma

IPC: G06F13/38 ,  G06F11/10 ,  G06F13/40

Abstract: In one embodiment, an apparatus includes: a first link layer circuit to perform link layer functionality for a first communication protocol; and a logical physical (logPHY) circuit coupled to the first link layer circuit via a logical PHY interface (LPIF) link, the logPHY circuit to communicate with the first link layer circuit in a flit mode in which the first information is communicated in a fixed width size and to communicate with another link layer circuit in a non-flit mode. Other embodiments are described and claimed.

公开(公告)号：US11971841B2

公开(公告)日：2024-04-30

申请号：US17008542

申请日：2020-08-31

Applicant: Intel Corporation

Inventor： Narasimha Lanka ,  Swadesh Choudhary ,  Mahesh Wagh ,  Lakshmipriya Seshan

IPC: G06F13/42 ,  G06F13/28

CPC classification number: G06F13/4286 ,  G06F13/287 ,  G06F13/4226

Abstract: An adapter is provided that includes a first interface to couple to a particular device, where link layer data is to be communicated over the first interface, and a second interface to couple to a physical layer (PHY) device. The PHY device includes wires to implement a physical layer of a link, and the link couples the adapter to another adapter via the PHY device. The second interface includes a data channel to communicate the link layer data over the physical layer, and a sideband channel to communicate sideband messages between the adapter and the other adapter over the physical layer. The adapter is to implement a logical PHY for the link.

公开(公告)号：US20230026906A1

公开(公告)日：2023-01-26

申请号：US17819390

申请日：2022-08-12

Applicant: Intel Corporation

Inventor： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.

公开(公告)号：US20220350769A1

公开(公告)日：2022-11-03

申请号：US17721413

申请日：2022-04-15

Applicant: Intel Corporation

Inventor： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

公开(公告)号：US11308018B2

公开(公告)日：2022-04-19

申请号：US17015963

申请日：2020-09-09

Applicant: Intel Corporation

Inventor： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

Abstract: Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

公开(公告)号：US20220012203A1

公开(公告)日：2022-01-13

申请号：US17485337

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Prahladachar Jayaprakash Bharadwaj ,  Bruce A. Tennant ,  Mahesh Wagh

IPC: G06F13/40 ,  G06F13/42

Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

公开(公告)号：US11144492B2

公开(公告)日：2021-10-12

申请号：US16812156

申请日：2020-03-06

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Prahladachar Jayaprakash Bharadwaj ,  Bruce A. Tennant ,  Mahesh Wagh

IPC: G06F13/40 ,  G06F13/42

Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

公开(公告)号：US11095556B2

公开(公告)日：2021-08-17

申请号：US15639393

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Mark S. Myers ,  Don Soltis ,  Ramacharan Sundararaman ,  Stephen R. Van Doren ,  Mahesh Wagh

IPC: H04L12/781 ,  H04L29/06 ,  H04L12/931 ,  H04L29/08

Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.