公开(公告)号：US11095556B2

公开(公告)日：2021-08-17

申请号：US15639393

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Mark S. Myers ,  Don Soltis ,  Ramacharan Sundararaman ,  Stephen R. Van Doren ,  Mahesh Wagh

IPC: H04L12/781 ,  H04L29/06 ,  H04L12/931 ,  H04L29/08

Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.

公开(公告)号：US10261904B2

公开(公告)日：2019-04-16

申请号：US15835384

申请日：2017-12-07

Applicant: Intel Corporation

Inventor： Chunhui Zhang ,  George Z. Chrysos ,  Edward T. Grochowski ,  Ramacharan Sundararaman ,  Chung-Lun Chan ,  Federico Ardanaz

IPC: G06F9/38 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0842

Abstract: Operations associated with a memory and operations associated with one or more functional units may be received. A dependency between the operations associated with the memory and the operations associated with one or more of the functional units may be determined. A first ordering may be created for the operations associated with the memory. Furthermore, a second ordering may be created for the operations associated with one or more of the functional units based on the determined dependency and the first operating of the operations associated with the memory.

公开(公告)号：US20210399982A1

公开(公告)日：2021-12-23

申请号：US17391557

申请日：2021-08-02

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Mark S. Myers ,  Don Soltis ,  Ramacharan Sundararaman ,  Stephen R. Van Doren ,  Mahesh Wagh

IPC: H04L12/781 ,  H04L29/06 ,  H04L12/931

Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.

公开(公告)号：US11729096B2

公开(公告)日：2023-08-15

申请号：US17391557

申请日：2021-08-02

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Mark S. Myers ,  Don Soltis ,  Ramacharan Sundararaman ,  Stephen R. Van Doren ,  Mahesh Wagh

IPC: H04L45/52 ,  H04L69/18 ,  H04L49/60 ,  H04L69/323

CPC classification number: H04L45/52 ,  H04L49/60 ,  H04L69/18 ,  H04L69/323

Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.

公开(公告)号：US20190102292A1

公开(公告)日：2019-04-04

申请号：US15720648

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Stephen R. Van Doren ,  Ramacharan Sundararaman

IPC: G06F12/06

Abstract: There is disclosed in an example a peripheral component interconnect express (PCIe) controller to provide coherent memory mapping between an accelerator memory and a host memory address space, having: a PCIe controller hub including extensions to provide a coherent accelerator interconnect (CAI) to provide bias-based coherency tracking between the accelerator memory and the host memory address space; wherein the extensions include: a mapping engine to provide opcode mapping between PCIe instructions and on-chip system fabric (OSF) instructions for the CAI; and a tunneling engine to provide scalable memory interconnect (SMI) tunneling of host memory operations to the accelerator memory via the CAI.

公开(公告)号：US11782866B2

公开(公告)日：2023-10-10

申请号：US17674030

申请日：2022-02-17

Applicant: Intel Corporation

Inventor： Stephen R. Van Doren ,  Rajesh M. Sankaran ,  David A. Koufaty ,  Ramacharan Sundararaman ,  Ishwar Agarwal

IPC: G06F13/42 ,  G06F13/14 ,  G06F13/38

CPC classification number: G06F13/4234 ,  G06F13/14 ,  G06F13/38

Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to detect a message to communicate via an interconnect coupled with a device capable of communication via a plurality of interconnect protocols, the plurality of interconnect protocols comprising a non-coherent interconnect protocol, a coherent interconnect protocol, and a memory interconnect protocol. Embodiments also include determining an interconnect protocol of the plurality of interconnect protocols to communicate the message via the interconnect based on the message, and providing the message to a multi-protocol multiplexer coupled with the interconnect, the multi-protocol multiplexer to communicate the message utilizing the interconnect protocol via the interconnect with the device.

公开(公告)号：US09875185B2

公开(公告)日：2018-01-23

申请号：US14327109

申请日：2014-07-09

Applicant: Intel Corporation

Inventor： Chunhui Zhang ,  George Z. Chrysos ,  Edward T. Grochowski ,  Ramacharan Sundararaman ,  Chung-Lun Chan ,  Federico Ardanaz

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0842 ,  G06F12/0817 ,  G06F12/0831 ,  G06F9/38 ,  G06F12/0806 ,  G06F12/0815

CPC classification number: G06F12/0842 ,  G06F9/38 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0835 ,  G06F2212/1016 ,  G06F2212/283 ,  G06F2212/621

Abstract: Operations associated with a memory and operations associated with one or more functional units may be received. A dependency between the operations associated with the memory and the operations associated with one or more of the functional units may be determined. A first ordering may be created for the operations associated with the memory. Furthermore, a second ordering may be created for the operations associated with one or more of the functional units based on the determined dependency and the first operating of the operations associated with the memory.

公开(公告)号：US09785556B2

公开(公告)日：2017-10-10

申请号：US14582148

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Ramacharan Sundararaman ,  Tracey L. Gustafson ,  Robert J. Safranek

IPC: G06F12/08 ,  G06F12/0831

CPC classification number: G06F12/0831 ,  G06F12/0833 ,  G06F2212/621 ,  Y02D10/13

Abstract: Methods and apparatus relating to techniques for Cross-Die Interface (CDI) snoop and/or go (or completion) message ordering are described. In one embodiment, the order of a snoop message and a completion message are determined based at least on status of two bits. The snoop and completion messages are exchanged between a first integrated circuit die and a second integrated circuit die. The first integrated circuit die and the second integrated circuit die are coupled through a first interface and a second interface and the snoop message and the completion message are exchanged over at least one of the first interface and the second interface. Other embodiments are also disclosed.

公开(公告)号：US20220197847A1

公开(公告)日：2022-06-23

申请号：US17674030

申请日：2022-02-17

Applicant: Intel Corporation

Inventor： Stephen R. Van Doren ,  Rajesh M. Sankaran ,  David A. Koufaty ,  Ramacharan Sundararaman ,  Ishwar Agarwal

IPC: G06F13/42 ,  G06F13/14

Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to detect a message to communicate via an interconnect coupled with a device capable of communication via a plurality of interconnect protocols, the plurality of interconnect protocols comprising a non-coherent interconnect protocol, a coherent interconnect protocol, and a memory interconnect protocol. Embodiments also include determining an interconnect protocol of the plurality of interconnect protocols to communicate the message via the interconnect based on the message, and providing the message to a multi-protocol multiplexer coupled with the interconnect, the multi-protocol multiplexer to communicate the message utilizing the interconnect protocol via the interconnect with the device.

公开(公告)号：US11204867B2

公开(公告)日：2021-12-21

申请号：US15720648

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Stephen R. Van Doren ,  Ramacharan Sundararaman

IPC: G06F12/00 ,  G06F12/06

Abstract: There is disclosed in an example a peripheral component interconnect express (PCIe) controller to provide coherent memory mapping between an accelerator memory and a host memory address space. The PCIe controller may include extensions to provide a coherent accelerator interconnect (CAI) to provide bias-based coherency tracking between the accelerator memory and the host memory address space. The extensions may include: a mapping engine to provide opcode mapping between PCIe instructions and on-chip system fabric (OSF) instructions for the CAI, a tunneling engine to provide scalable memory interconnect (SMI) tunneling of host memory operations to the accelerator memory via the CAI, host-bias-to-device-bias (HBDB) flip engine to enable the accelerator to flush a host cache line, and a QoS engine comprising a plurality of virtual channels.