公开(公告)号：US20180004595A1

公开(公告)日：2018-01-04

申请号：US15201438

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Ron Gabor ,  Hisham Shafi ,  Sergiu Ghetie ,  Mohan J. Kumar ,  Theodros Yigzaw ,  Sarathy Jayakumar ,  Neeraj S. Upasani

IPC: G06F11/10 ,  G06F12/0893 ,  G06F12/1045 ,  G06F12/0875 ,  G06F3/06

CPC classification number: G06F11/1048 ,  G06F11/0721

Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US09792190B2

公开(公告)日：2017-10-17

申请号：US14752585

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  George Vergis

IPC: G06F11/20 ,  G06F3/06 ,  G06F11/30

CPC classification number: G06F11/2069 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0685 ,  G06F11/00 ,  G06F11/3034 ,  G06F11/3058 ,  G06F2201/82

Abstract: Embodiments are generally directed to high capacity energy backed memory with off device storage. A memory device includes a circuit board; multiple memory chips that are installed on the circuit board; a controller to provide for backing up contents of the memory chips when a power loss condition is detected; a connection to a backup energy source; and a connection to a backup data storage that is separate from the memory device.

公开(公告)号：US09645829B2

公开(公告)日：2017-05-09

申请号：US14319361

申请日：2014-06-30

Applicant: INTEL CORPORATION

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Adam J. Brooks ,  George Vergis

IPC: G06F11/14 ,  G06F9/44 ,  G06F11/20

CPC classification number: G06F9/4401 ,  G06F11/1441 ,  G06F11/2015

Abstract: Examples may include communicating with a controller for a non-volatile dual in-line memory module through a system management bus (SMBus) interface. In some examples, selective assertion of bits maintained in registers accessible through the SMBus interface may enable communication with the controller. The selective assertion may be based on a register map.

公开(公告)号：US20170046208A1

公开(公告)日：2017-02-16

申请号：US15178159

申请日：2016-06-09

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Mohan J. Kumar ,  Balint Fleischer

IPC: G06F9/52 ,  G06F12/1081 ,  G06F9/46 ,  G06F13/40 ,  G06F13/16 ,  G11C14/00

CPC classification number: G06F9/52 ,  G06F3/0619 ,  G06F3/0661 ,  G06F3/0688 ,  G06F9/467 ,  G06F11/2017 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/1081 ,  G06F13/1663 ,  G06F13/32 ,  G06F13/4022 ,  G06F2212/1056 ,  G11C14/009

Abstract: An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency.

Abstract translation: 这里描述了一种用于提供数据一致性的装置。 该装置包括全局持久存储器。 使用包含输入/输出（I / O）语义和内存语义的协议来访问全局永久存储器。 该装置还包括反射存储区域。 反射的存储器区域是全局持久存储器的一部分，并且多个节点的每个节点将反射的存储器区域映射到不可高速缓存的空间中。 此外，该装置包括信号量存储器。 信号量存储器为强制数据一致性提供硬件辅助。

公开(公告)号：US09372752B2

公开(公告)日：2016-06-21

申请号：US14142726

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Mohan J. Kumar ,  Balint Fleischer

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/20 ,  G06F12/08 ,  G06F15/16

CPC classification number: G06F11/2094 ,  G06F11/108 ,  G06F11/1088 ,  G06F11/2043 ,  G06F11/2087 ,  G06F11/2092 ,  G06F11/2097 ,  G06F12/08 ,  G06F12/0833 ,  G06F12/0837 ,  G06F15/16 ,  G06F2201/805 ,  G06F2201/82

Abstract: An apparatus for coherent shared memory across multiple clusters is described herein. The apparatus includes a fabric memory controller and one or more nodes. The fabric memory controller manages access to a shared memory region of each node such that each shared memory region is accessible using load store semantics, even in response to failure of the node. The apparatus also includes a global memory, wherein each shared memory region is mapped to the global memory by the fabric memory controller.

Abstract translation: 本文描述了跨多个集群的相干共享存储器的装置。 该装置包括织物存储器控制器和一个或多个节点。 织物存储器控制器管理对每个节点的共享存储器区域的访问，使得即使响应于节点的故障，每个共享存储器区域也可以使用加载存储器语义来访问。 该设备还包括全局存储器，其中每个共享存储器区域被结构存储器控制器映射到全局存储器。

公开(公告)号：US09141454B2

公开(公告)日：2015-09-22

申请号：US13728217

申请日：2012-12-27

Applicant: Intel Corporation

Inventor： Ashok Raj ,  John G. Holm ,  Gilbert Neiger ,  Rajesh M. Sankaran ,  Mohan J. Kumar

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/006 ,  G06F11/0715 ,  G06F11/0772 ,  G06F11/0793

Abstract: Embodiments of an invention for signaling software recoverable errors are disclosed. In one embodiment, a processor includes a first unit, a programmable indicator, and a second unit. The first unit is to detect a poison error. The programmable indicator is to indicate whether the poison error is signaled as a machine check error or as one of a fault and a system management interrupt. The second unit is to signal the poison error as one of a fault and a system management error responsive to the programmable indicator.

Abstract translation: 公开了用于信令软件可恢复错误的发明的实施例。 在一个实施例中，处理器包括第一单元，可编程指示器和第二单元。 第一个单位是检测毒物的错误。 可编程指示灯是指示是否发出毒物误差作为机器检查错误或作为故障和系统管理中断之一发出信号。 第二个单元将响应于可编程指示器的毒性错误信号作为故障之一和系统管理错误。

公开(公告)号：US12008359B2

公开(公告)日：2024-06-11

申请号：US16790488

申请日：2020-02-13

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Michael A. Rothman

IPC: G06F8/656 ,  G06F9/4401 ,  G06F21/57

CPC classification number: G06F8/656 ,  G06F9/4401 ,  G06F21/572 ,  G06F2221/033

Abstract: Examples described herein provide a central processing unit (CPU) to reserve a region of memory for use to store both a boot firmware code and a second boot firmware code and to perform the second boot firmware code without reboot. The reserved region of memory can be a region that is not configured for access by an operating system (OS). The reserved region of memory comprises System Management Random Access Memory (SMRAM). If a first interrupt handler is not overwritten after a second boot firmware code is stored, the CPU can roll back to use of the first interrupt handler.

公开(公告)号：US11941391B2

公开(公告)日：2024-03-26

申请号：US16841410

申请日：2020-04-06

Applicant: Intel Corporation

Inventor： Mohan J. Kumar ,  Sarathy Jayakumar ,  Chuan Song ,  Ruixia Li ,  Xiaojin Yuan ,  Haiyue Wang ,  Chong Han

IPC: G06F8/656 ,  G06F8/654 ,  G06F9/4401 ,  G06F9/445 ,  G06F9/455

CPC classification number: G06F8/656 ,  G06F8/654 ,  G06F9/4401 ,  G06F9/44557 ,  G06F9/45541

Abstract: A microcode (uCode) hot-upgrade method for bare metal cloud deployment and associated apparatus. The uCode hot-upgrade method applies a uCode patch to a firmware storage device (e.g., BIOS SPI flash) through an out-of-band controller (e.g., baseboard management controller (BMC)). In conjunction with receiving a uCode patch, a uCode upgrade interrupt service is triggered to upgrade uCode for one or more CPUs in a bare-metal cloud platform during runtime of a tenant host operating system (OS) using an out-of-bound process. This innovation enables cloud service providers to deploy uCode hot-patches to bare metal servers for persistent storage and live-patch without touching the tenant operating system environment.

公开(公告)号：US11922220B2

公开(公告)日：2024-03-05

申请号：US17255588

申请日：2019-04-16

Applicant: Intel Corporation

Inventor： Mohammad R. Haghighat ,  Kshitij Doshi ,  Andrew J. Herdrich ,  Anup Mohan ,  Ravishankar R. Iyer ,  Mingqiu Sun ,  Krishna Bhuyan ,  Teck Joo Goh ,  Mohan J. Kumar ,  Michael Prinke ,  Michael Lemay ,  Leeor Peled ,  Jr-Shian Tsai ,  David M. Durham ,  Jeffrey D. Chamberlain ,  Vadim A. Sukhomlinov ,  Eric J. Dahlen ,  Sara Baghsorkhi ,  Harshad Sane ,  Areg Melik-Adamyan ,  Ravi Sahita ,  Dmitry Yurievich Babokin ,  Ian M. Steiner ,  Alexander Bachmutsky ,  Anil Rao ,  Mingwei Zhang ,  Nilesh K. Jain ,  Amin Firoozshahian ,  Baiju V. Patel ,  Wenyong Huang ,  Yeluri Raghuram

IPC: G06F9/50 ,  G06F9/52 ,  G06F11/30 ,  G06F11/34 ,  G06F21/53 ,  G06F21/56 ,  G06F21/60 ,  G06N20/00

CPC classification number: G06F9/5061 ,  G06F9/52 ,  G06F11/302 ,  G06F11/3495 ,  G06F21/53 ,  G06F21/604 ,  G06F21/56 ,  G06F2209/521 ,  G06F2221/033 ,  G06N20/00

Abstract: Embodiments of systems, apparatuses and methods provide enhanced function as a service (FaaS) to users, e.g., computer developers and cloud service providers (CSPs). A computing system configured to provide such enhanced FaaS service include one or more controls architectural subsystems, software and orchestration subsystems, network and storage subsystems, and security subsystems. The computing system executes functions in response to events triggered by the users in an execution environment provided by the architectural subsystems, which represent an abstraction of execution management and shield the users from the burden of managing the execution. The software and orchestration subsystems allocate computing resources for the function execution by intelligently spinning up and down containers for function code with decreased instantiation latency and increased execution scalability while maintaining secured execution. Furthermore, the computing system enables customers to pay only when their code gets executed with a granular billing down to millisecond increments.

公开(公告)号：US11748172B2

公开(公告)日：2023-09-05

申请号：US15858542

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Mohan J. Kumar ,  Murugasamy K. Nachimuthu

IPC: H04L41/5025 ,  G06F11/34 ,  B25J15/00 ,  G06F1/18 ,  G06F1/20 ,  G06F15/78 ,  H05K7/14 ,  H05K7/18 ,  H05K7/20 ,  H04L67/1008 ,  H04L41/5019 ,  H04L41/14 ,  G06F9/50 ,  H04L41/0896 ,  G06N3/063 ,  G06F21/10 ,  G06Q30/0283 ,  G06F9/44 ,  G06F13/40 ,  G06Q10/0631 ,  H04L49/40 ,  G06F9/48 ,  H04L9/40

CPC classification number: G06F9/5088 ,  B25J15/0014 ,  G06F1/183 ,  G06F1/20 ,  G06F9/505 ,  G06F11/3442 ,  G06F15/7807 ,  G06F15/7867 ,  H04L41/5025 ,  H04L67/1008 ,  H05K7/1489 ,  H05K7/18 ,  H05K7/20209 ,  H05K7/20736 ,  G06F9/44 ,  G06F9/4856 ,  G06F9/5061 ,  G06F13/4022 ,  G06F21/105 ,  G06F2200/201 ,  G06N3/063 ,  G06Q10/0631 ,  G06Q30/0283 ,  H04L41/0896 ,  H04L41/14 ,  H04L41/5019 ,  H04L49/40 ,  H04L63/0428 ,  H05K7/1498

Abstract: Technologies for providing efficient pooling for a system that includes a hyper converged infrastructure. A sled of the system includes a network interface controller that includes a first bridge logic unit to communicatively couple to a network of bridge logic units. The first bridge logic unit is further to obtain, from a requestor device, a request to access a requested device, determine whether the requested device is on the present sled or on a remote sled different from the present sled, selectively power on, in response to a determination that the requested device is located on the present sled, the requested device, communicate, in response to a determination that the requested device is on the remote sled, with a second bridge logic unit of the remote sled, and provide, to the requestor device through the first bridge logic unit, access to the requested device.