公开(公告)号：US20170070381A1

公开(公告)日：2017-03-09

申请号：US14846711

申请日：2015-09-04

Applicant: Intel Corporation

Inventor： Satheesh Chellappan

IPC: H04L12/24 ,  H04L12/26 ,  H04L29/08

CPC classification number: H04L41/0654 ,  H04L41/0672 ,  H04L43/0823 ,  H04L69/323 ,  H04L69/324

Abstract: An override subsystem on the host side of a serial data link between the host and a peripheral detects and diagnoses link errors by comparing the states of the port's link-layer component and physical layer. An override controller accesses a data-store containing stored policies for responding to particular errors. After selecting the appropriate policy, the override controller takes control of the physical layer, the link-layer component, or both, reconfigures them according to the policy to correct the errors, and returns control of the physical layer to the host controller and link-layer component. As well as error recovery, the override subsystem may be used by applications or drivers to asynchronously manage power consumed by the link.

Abstract translation: 通过比较端口的链路层组件和物理层的状态，在主机和外设之间的串行数据链路的主机侧的覆盖子系统检测并诊断链路错误。 覆盖控制器访问包含用于响应特定错误的存储策略的数据存储。 在选择适当的策略之后，覆盖控制器控制物理层，链路层组件或两者，根据策略重新配置以纠正错误，并将物理层的控制返回给主机控制器和链路层， 层组件。 除了错误恢复之外，应用程序或驱动程序可以使用覆盖子系统来异步管理链路消耗的功耗。

公开(公告)号：US20220179821A1

公开(公告)日：2022-06-09

申请号：US17680623

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Satheesh Chellappan ,  Haran Thanigasalam

IPC: G06F13/42 ,  G06F13/24 ,  G06F13/40 ,  G06F13/36

Abstract: In one embodiment, a system includes a host system-on-chip (SoC) comprising vision processing circuitry and a camera connected to the host SoC through an Inter-Integrated Circuit (I3C) bus. The camera includes circuitry to generate image data and transmit an interrupt signal to the host SoC over the I3C bus indicating the image data is ready for transfer. The host SoC vision processing circuitry is to transmit a read message to the camera over the I3C bus based on the interrupt signal and receive a set of line payload packets including the image data over the I3C bus based on the read message.

公开(公告)号：US10788533B2

公开(公告)日：2020-09-29

申请号：US16116675

申请日：2018-08-29

Applicant: Intel Corporation

Inventor： Kishore Kasichainula ,  Satheesh Chellappan ,  Lay Chen Ong ,  Harish G. Kamat

IPC: G01R31/3185 ,  G01R31/317 ,  G01R31/319

Abstract: Technology for bypass testing of an integrated circuit using a testing device. The testing device comprising a port configured to connect to an integrated circuit before the integrated circuit is packaged into an end product. The testing device further comprising a controller with architecture configured to bypass a training process designed to be initiated when the integrated circuit is first connected to the port and the port is powered on, confirm a connection between the integrated circuit and the testing device, send a test pattern to the integrated circuit to execute; and receive results from the integrated circuit executing the test pattern.

公开(公告)号：US10366017B2

公开(公告)日：2019-07-30

申请号：US15941273

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Darren Abramson ,  David Hines ,  Alberto Martinez ,  Adeel Aslam ,  John Howard ,  Shanthanand R. Kutuva ,  Karthi R. Vadivelu ,  Kar Leong Wong ,  Satheesh Chellappan

IPC: G06F13/38 ,  G06F13/10 ,  G06F3/06

Abstract: An example apparatus includes: a host controller offload capability detector to determine that a media stream offload capability is available in the peripheral interface host controller; a media stream offload arbiter to send a media stream offload request to a media processor manager based on the media stream offload capability and based on a peripheral device being connected to the peripheral interface host controller; and an endpoint mapper to generate an endpoint table entry corresponding to the peripheral device, the endpoint table entry to assign a first communication interface of the peripheral interface host controller to transfer a media stream corresponding to the peripheral device between the media processor and the peripheral interface host controller without the media stream being routed to an application processor that is in circuit with the peripheral interface host controller and in circuit with the media processor.

公开(公告)号：US20190101592A1

公开(公告)日：2019-04-04

申请号：US16116675

申请日：2018-08-29

Applicant: Intel Corporation

Inventor： Kishore Kasichainula ,  Satheesh Chellappan ,  Lay Chen Ong ,  Harish G. Kamat

IPC: G01R31/3185 ,  G01R31/317

Abstract: Technology for bypass testing of an integrated circuit using a testing device. The testing device comprising a port configured to connect to an integrated circuit before the integrated circuit is packaged into an end product. The testing device further comprising a controller with architecture configured to bypass a training process designed to be initiated when the integrated circuit is first connected to the port and the port is powered on, confirm a connection between the integrated circuit and the testing device, send a test pattern to the integrated circuit to execute; and receive results from the integrated circuit executing the test pattern.

公开(公告)号：US10181975B2

公开(公告)日：2019-01-15

申请号：US14846711

申请日：2015-09-04

Applicant: Intel Corporation

Inventor： Satheesh Chellappan

IPC: H04L12/24 ,  H04L12/26 ,  H04L29/08

Abstract: An override subsystem on the host side of a serial data link between the host and a peripheral detects and diagnoses link errors by comparing the states of the port's link-layer component and physical layer. An override controller accesses a data-store containing stored policies for responding to particular errors. After selecting the appropriate policy, the override controller takes control of the physical layer, the link-layer component, or both, reconfigures them according to the policy to correct the errors, and returns control of the physical layer to the host controller and link-layer component. As well as error recovery, the override subsystem may be used by applications or drivers to asynchronously manage power consumed by the link.

公开(公告)号：US10127162B2

公开(公告)日：2018-11-13

申请号：US15196832

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Suketu U. Bhatt ,  Lakshminarayana Pappu ,  Satheesh Chellappan

IPC: G06F13/10 ,  G06F13/20 ,  G06F13/40 ,  G06F13/42

Abstract: Described is a host interface, a device interface, a downstream translation circuitry, an upstream translation circuitry, and a host line-state state machine. The host interface may comprise a host line-state output. The device interface may comprise a device line-state output. The downstream translation circuitry may be operable to process a transaction received on the host interface and to generate a transaction for the device interface. The upstream translation circuitry may be operable to process a transaction received on the device interface and to generate a transaction for the host interface. The host line-state state machine may be operable to set the host line-state output to a value that is one of: an SE0-state value, a J-state value, or a K-state value.

公开(公告)号：US20180188321A1

公开(公告)日：2018-07-05

申请号：US15394666

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Suketu U. Bhatt ,  Satheesh Chellappan

IPC: G01R31/317 ,  G01R31/3177

Abstract: Techniques and mechanisms for providing on-chip link control functionality to facilitate emulation of a communication. In an embodiment, an integrated circuit (IC) chip includes a physical layer (PHY) which supports communication compatible with a high-speed serial interface standard. A link controller of the IC chip is coupled between the PHY and an interconnect architecture which variously couples a host and other resources of the IC chip to each other. A test controller of the IC chip signals a test mode to implement a loopback path of the link controller in lieu of one or more functional paths for communication with the PHY. In another embodiment, signal output by the loopback path emulate a communication from a resource other than the test controller.

公开(公告)号：US20170185550A1

公开(公告)日：2017-06-29

申请号：US14757830

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Satheesh Chellappan ,  Chunyu Zhang

IPC: G06F13/37 ,  G06F1/12 ,  G06F1/26 ,  G06F13/42

CPC classification number: G06F13/37 ,  G06F13/4226 ,  Y02D10/14 ,  Y02D10/151

Abstract: In a system where multiple controllers share a link interface but are not all (1) compatible with the same configuration of the physical layer or (2) using the same clocking, a configuration arbitration subsystem intercepts, organizes, and re-clocks configuration-access requests from the various controller agents. Priorities are assigned according to stored policies. The configuration arbiter grants configuration access to the top-priority agent, synchronizing the agent's message with the arbiter's clock. Lower-priority agents' messages are stored in command queues until they ascend to top priority. Besides preventing timing conflicts and streamlining the coordination of clocks, the configuration arbiter may provide access to physical-layer registers beyond the controllers' built-in capabilities to further optimize configuration.

公开(公告)号：US09280510B2

公开(公告)日：2016-03-08

申请号：US14600470

申请日：2015-01-20

Applicant: Intel Corporation

Inventor： Sridharan Ranganathan ,  David J. Harriman ,  Anoop Mukker ,  Satheesh Chellappan ,  Karthi R. Vadivelu ,  Shalini Sharma ,  Zeeshan Sarwar

IPC: G06F13/36 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4291 ,  G06F13/4027 ,  G06F13/426 ,  Y02D10/14 ,  Y02D10/151

Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface.

Abstract translation: 用于本文提供的设备中的单元之间的低功率，高带宽通信的接口。 接口包括USB 3.0系统接口和配置为便于USB 3.0系统接口和M-PHY接口之间的通信的SuperSpeed芯片间（SSIC）协议适配器。