公开(公告)号：US20240105508A1

公开(公告)日：2024-03-28

申请号：US17935647

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Jitendra Kumar Jha ,  Justin Mueller ,  Nazila Haratipour ,  Gilbert W. Dewey ,  Chi-Hing Choi ,  Jack T. Kavalieros ,  Siddharth Chouksey ,  Nancy Zelick ,  Jean-Philippe Turmaud ,  I-Cheng Tung ,  Blake Bluestein

IPC: H01L21/768 ,  H01L29/49

CPC classification number: H01L21/76856 ,  H01L21/76837 ,  H01L21/76877 ,  H01L29/4908

Abstract: Disclosed herein are integrated circuit (IC) devices with contacts using nitridized molybdenum. For example, a contact arrangement for an IC device may include a semiconductor material and a contact extending into a portion of the semiconductor material. The contact may include molybdenum. The molybdenum may be in a first layer and a second layer, where the second layer may further include nitrogen. The first layer may have a thickness between about 5 nanometers and 16 nanometers, and the second layer may have a thickness between about 0.5 nanometers to 2.5 nanometers. The contact may further include a fill material (e.g., an electrically conductive material) and the second layer may be in contact with the fill material. The molybdenum may have a low resistance, and thus may improve the electrical performance of the contact. The nitridized molybdenum may prevent oxidation during the fabrication of the contact.

公开(公告)号：US11923421B2

公开(公告)日：2024-03-05

申请号：US17869622

申请日：2022-07-20

Applicant: Intel Corporation

Inventor： Siddharth Chouksey ,  Glenn Glass ,  Anand Murthy ,  Harold Kennel ,  Jack T. Kavalieros ,  Tahir Ghani ,  Ashish Agrawal ,  Seung Hoon Sung

IPC: H01L31/072 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L31/109

CPC classification number: H01L29/165 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

公开(公告)号：US20240006533A1

公开(公告)日：2024-01-04

申请号：US17856982

申请日：2022-07-02

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Siddharth Chouksey ,  Nazila Haratipour ,  Christopher Jezewski ,  Jitendra Kumar Jha ,  Ilya V. Karpov ,  Matthew V. Metz ,  Arnab Sen Gupta ,  I-Cheng Tung ,  Nancy Zelick ,  Chi-Hing Choi ,  Dan S. Lavric

IPC: H01L29/78 ,  H01L29/167

CPC classification number: H01L29/785 ,  H01L29/167

Abstract: Contacts to p-type source/drain regions comprise a boride, indium, or gallium metal compound layer. The boride, indium, or gallium metal compound layers can aid in forming thermally stable low resistance contacts. A boride, indium, or gallium metal compound layer is positioned between the source/drain region and the contact metal layer. A boride, indium, or gallium metal compound layer can be used in contacts contacting p-type source/drain regions comprising boron, indium, or gallium as the primary dopant, respectively. The boride, indium, or gallium metal compound layers prevent diffusion of boron, indium, or gallium from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation. Boride, indium, or gallium metal contact layers can also reduce the amount of silicide that forms in source/drain regions during processing by limiting contact metal diffusion into source/drain regions.

公开(公告)号：US20230187553A1

公开(公告)日：2023-06-15

申请号：US17546461

申请日：2021-12-09

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Gilbert W. Dewey ,  Siddharth Chouksey ,  Nazila Haratipour ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Scott B. Clendenning ,  Jason C. Retasket ,  Edward O. Johnson, JR.

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L29/78696 ,  H01L29/66742

Abstract: Described herein are integrated circuit devices with source and drain (S/D) contacts with barrier regions. The S/D contacts conduct current to and from semiconductor devices, e.g., to the source and drain regions of a transistor. The barrier regions are formed between the S/D region and an inner conductive structure and reduce the Schottky barrier height between the S/D region and the contact. The barrier regions may include one or more carbon layers and one or more metal layers. A metal layer may include niobium, tantalum, aluminum, or titanium.

公开(公告)号：US11532706B2

公开(公告)日：2022-12-20

申请号：US16369760

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand Murthy ,  Susmita Ghose ,  Siddharth Chouksey

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/32 ,  H01L29/165 ,  H01L29/167 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/027 ,  H01L21/66

Abstract: Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, the fin including a defect modification layer on a first semiconductor layer, and a second semiconductor layer on the defect modification layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

公开(公告)号：US20200091287A1

公开(公告)日：2020-03-19

申请号：US16131520

申请日：2018-09-14

Applicant: INTEL CORPORATION

Inventor： Glenn Glass ,  Anand Murthy ,  Cory Bomberger ,  Tahir Ghani ,  Jack Kavalieros ,  Siddharth Chouksey ,  Seung Hoon Sung ,  Biswajeet Guha ,  Ashish Agrawal

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8238

Abstract: A semiconductor structure has a substrate including silicon and a layer of relaxed buffer material on the substrate with a thickness no greater than 300 nm. The buffer material comprises silicon and germanium with a germanium concentration from 20 to 45 atomic percent. A source and a drain are on top of the buffer material. A body extends between the source and drain, where the body is monocrystalline semiconductor material comprising silicon and germanium with a germanium concentration of at least 30 atomic percent. A gate structure is wrapped around the body.

公开(公告)号：US20240006494A1

公开(公告)日：2024-01-04

申请号：US17856206

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Gilbert Dewey ,  Nancy Zelick ,  Siddharth Chouksey ,  I-Cheng Tung ,  Arnab Sen Gupta ,  Jitendra Kumar Jha ,  Chi-Hing Choi ,  Matthew V. Metz ,  Jack T. Kavalieros

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/41733 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/6656

Abstract: Semiconductor structures having a source and/or drain with a refractory metal cap, and methods of forming the same, are described herein. In one example, a semiconductor structure includes a channel, a gate, a source, and a drain. The source and drain contain silicon and germanium, and one or both of the source and drain are capped with a semiconductor cap and a refractory metal cap. The semiconductor cap is on the source and/or drain and contains germanium and boron. The refractory metal cap is on the semiconductor cap and contains a refractory metal.

公开(公告)号：US20230139255A1

公开(公告)日：2023-05-04

申请号：US17517076

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Ashish Agrawal ,  Gilbert Dewey ,  Siddharth Chouksey ,  Jack T. Kavalieros ,  Cheng-Ying Huang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/165 ,  H01L27/092

Abstract: A gate-all-around transistor device includes a body including a semiconductor material, and a gate structure at least in part wrapped around the body. The gate structure includes a gate electrode and a gate dielectric between the body and the gate electrode. The body is between a source region and a drain region. A first spacer is between the source region and the gate electrode, and a second spacer is between the drain region and the gate electrode. In an example, the first and second spacers include germanium and oxygen. The body can be, for instance, a nanoribbon, nanosheet, or nanowire.

公开(公告)号：US11450739B2

公开(公告)日：2022-09-20

申请号：US16131520

申请日：2018-09-14

Applicant: INTEL CORPORATION

Inventor： Glenn Glass ,  Anand Murthy ,  Cory Bomberger ,  Tahir Ghani ,  Jack Kavalieros ,  Siddharth Chouksey ,  Seung Hoon Sung ,  Biswajeet Guha ,  Ashish Agrawal

IPC: H01L29/06 ,  H01L21/82 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/161 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure has a substrate including silicon and a layer of relaxed buffer material on the substrate with a thickness no greater than 300 nm. The buffer material comprises silicon and germanium with a germanium concentration from 20 to 45 atomic percent. A source and a drain are on top of the buffer material. A body extends between the source and drain, where the body is monocrystalline semiconductor material comprising silicon and germanium with a germanium concentration of at least 30 atomic percent. A gate structure is wrapped around the body.

公开(公告)号：US11437472B2

公开(公告)日：2022-09-06

申请号：US16022510

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Siddharth Chouksey ,  Glenn Glass ,  Anand Murthy ,  Harold Kennel ,  Jack T. Kavalieros ,  Tahir Ghani ,  Ashish Agrawal ,  Seung Hoon Sung

IPC: H01L31/072 ,  H01L31/109 ,  H01L29/165 ,  H01L21/8234 ,  H01L29/06 ,  H01L27/088

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.