公开(公告)号：US11923290B2

公开(公告)日：2024-03-05

申请号：US16913859

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Siddharth Chouksey ,  Gilbert Dewey ,  Nazila Haratipour ,  Mengcheng Lu ,  Jitendra Kumar Jha ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Scott B Clendenning ,  Eric Charles Mattson

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/78

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53266 ,  H01L29/785 ,  H01L2029/7858

Abstract: Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal.

公开(公告)号：US11735670B2

公开(公告)日：2023-08-22

申请号：US17497864

申请日：2021-10-08

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/161 ,  H01L27/088 ,  H01L29/775 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78684 ,  H01L29/78696

Abstract: Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.

公开(公告)号：US11233148B2

公开(公告)日：2022-01-25

申请号：US16649304

申请日：2017-11-06

Applicant: INTEL CORPORATION

Inventor： Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Seung Hoon Sung ,  Siddharth Chouksey ,  Harold W. Kennel ,  Dipanjan Basu ,  Ashish Agrawal ,  Glenn A. Glass ,  Tahir Ghani ,  Anand S. Murthy

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66

Abstract: Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials.

公开(公告)号：US20210005748A1

公开(公告)日：2021-01-07

申请号：US16641022

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423

Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.

公开(公告)号：US20200266296A1

公开(公告)日：2020-08-20

申请号：US16649304

申请日：2017-11-06

Applicant: INTEL CORPORATION

Inventor： Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Seung Hoon Sung ,  Siddharth Chouksey ,  Harold W. Kennel ,  Dipanjan Basu ,  Ashish Agrawal ,  Glenn A. Glass ,  Tahir Ghani ,  Anand S. Murthy

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/205 ,  H01L21/02 ,  H01L29/66

Abstract: Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials.

公开(公告)号：US20200258982A1

公开(公告)日：2020-08-13

申请号：US16649716

申请日：2017-12-26

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

Abstract: Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.

公开(公告)号：US12272727B2

公开(公告)日：2025-04-08

申请号：US18440526

申请日：2024-02-13

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand Murthy ,  Susmita Ghose ,  Siddharth Chouksey

IPC: H01L29/08 ,  H01L21/02 ,  H01L21/027 ,  H01L21/306 ,  H01L21/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/165 ,  H01L29/167 ,  H01L29/32 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, the fin including a defect modification layer on a first semiconductor layer, and a second semiconductor layer on the defect modification layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

公开(公告)号：US12119387B2

公开(公告)日：2024-10-15

申请号：US17033471

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Nazila Haratipour ,  Siddharth Chouksey ,  Jack T. Kavalieros ,  Jitendra Kumar Jha ,  Matthew V. Metz ,  Mengcheng Lu ,  Anand S. Murthy ,  Koustav Ganguly ,  Ryan Keech ,  Glenn A. Glass ,  Arnab Sen Gupta

IPC: H01L29/45 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/45 ,  H01L21/28518 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.

公开(公告)号：US11990513B2

公开(公告)日：2024-05-21

申请号：US17988612

申请日：2022-11-16

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand Murthy ,  Susmita Ghose ,  Siddharth Chouksey

IPC: H01L29/08 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L29/10 ,  H01L29/165 ,  H01L29/167 ,  H01L29/32 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/027 ,  H01L21/66

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/167 ,  H01L29/32 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/0276 ,  H01L21/30625 ,  H01L22/26

Abstract: Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, the fin including a defect modification layer on a first semiconductor layer, and a second semiconductor layer on the defect modification layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

公开(公告)号：US20240006488A1

公开(公告)日：2024-01-04

申请号：US17856620

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Gilbert Dewey ,  Nancy Zelick ,  Siddharth Chouksey ,  I-Cheng Tung ,  Arnab Sen Gupta ,  Jitendra Kumar Jha ,  David Kohen ,  Natalie Briggs ,  Chi-Hing Choi ,  Matthew V. Metz ,  Jack T. Kavalieros

IPC: H01L29/08 ,  H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L21/033

CPC classification number: H01L29/0847 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/7851 ,  H01L29/401 ,  H01L29/66795 ,  H01L21/0332

Abstract: In one embodiment, layers comprising Carbon (e.g., Silicon Carbide) are on source/drain regions of a transistor, e.g., before gate formation and metallization, and the layers comprising Carbon are later removed in the manufacturing process to form electrical contacts on the source/drain regions.