公开(公告)号：US20200343049A1

公开(公告)日：2020-10-29

申请号：US16392028

申请日：2019-04-23

Applicant: Intel Corporation

Inventor： Sameer PAITAL ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Kristof DARMAWIKARTA

IPC: H01G4/33 ,  H01L23/498 ,  H01L23/538 ,  H01G4/30 ,  H01G4/38 ,  H01G4/224 ,  H01L23/00

Abstract: Embodiments disclosed herein include an electronic package and methods of forming an electronic package. In an embodiment, the electronic package comprises a package substrate, an organic layer over the package substrate, and a capacitor embedded in the organic layer. In an embodiment, the capacitor comprises, a first electrode, where the first electrode comprises a seam between a first conductive layer and a second conductive layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer.

公开(公告)号：US20200005990A1

公开(公告)日：2020-01-02

申请号：US16024721

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Sameer PAITAL ,  Srinivas PIETAMBARAM ,  Yonggang LI ,  Bai NIE ,  Kristof DARMAWIKARTA ,  Gang DUAN

IPC: H01F27/28 ,  H01F27/24 ,  H01L21/48 ,  H01L25/16 ,  H01L23/498 ,  H01F41/04 ,  H01L49/02

Abstract: Embodiments herein relate to systems, apparatuses, or processes for embedding a magnetic core or a magnetic inductor in a substrate layer by applying a copper layer to a portion of the substrate layer, creating a structure in the substrate layer on top of at least part of the copper layer to identify a defined region within the substrate layer, and inserting a magnetic paste into the defined region where the copper layer identifies a side of the defined region and where the structure is to contain the magnetic paste within the defined region while the magnetic paste cures.

公开(公告)号：US20190295967A1

公开(公告)日：2019-09-26

申请号：US15933599

申请日：2018-03-23

Applicant: Intel Corporation

Inventor： Kirstof DARMAWIKARTA ,  Srinivas PIETAMBARAM ,  Prithwish CHATTERJEE ,  Sri Ranga Sai BOYAPATI ,  Wei Lun JEN

IPC: H01L23/64 ,  H01F41/04 ,  H01F27/28 ,  H01F1/14 ,  H01F1/34 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Techniques for fabricating a semiconductor package comprising inductor features and a magnetic film are described. For one technique, fabricating a package includes: forming inductor features comprising a pad and a conductive line on a first build-up layer; forming a raised pad structure on the first build-up layer by fabricating a pillar structure on the pad, wherein a size of the pillar structure is approximately equal or equal to a corresponding size of the pad such that the pillar structure and the pad are aligned or minimally misaligned relative to each other; encapsulating the inductor features and the raised pad structure in a magnetic film; planarizing the magnetic film until top surfaces of the raised pad structure and magnetic film are co-planar; depositing an additional layer on the top surfaces; and forming a via on the raised pad structure by removing portions of the additional layer above the raised pad structure.

公开(公告)号：US20250015003A1

公开(公告)日：2025-01-09

申请号：US18887990

申请日：2024-09-17

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Rahul MANEPALLI ,  Gang DUAN

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

公开(公告)号：US20230405976A1

公开(公告)日：2023-12-21

申请号：US18241067

申请日：2023-08-31

Applicant: Intel Corporation

Inventor： Jieying KONG ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Patrick QUACH ,  Dilan SENEVIRATNE

IPC: B32B17/10 ,  B32B15/20 ,  H01L23/00 ,  H01L23/48

CPC classification number: B32B17/10192 ,  B32B15/20 ,  H01L24/09 ,  H01L23/481 ,  H01L2224/02379

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to a manufacturing process flow for packages that include one or more glass layers that include patterning features, such as electrically conductive traces, RDLs, and vias within the packages. In embodiments, a package may include a glass layer with a first side and a second side opposite the first side, where the glass layer is a dielectric layer. The package may include another layer coupled with the first side of the glass layer, and a pattern on the second side of the glass layer to receive a deposited material in at least a portion of the pattern.

公开(公告)号：US20220254721A1

公开(公告)日：2022-08-11

申请号：US17732365

申请日：2022-04-28

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Rahul MANEPALLI ,  Gang DUAN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

公开(公告)号：US20220238458A1

公开(公告)日：2022-07-28

申请号：US17716947

申请日：2022-04-08

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Gang DUAN ,  Deepak KULKARNI ,  Rahul MANEPALLI ,  Xiaoying GUO

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

公开(公告)号：US20210066447A1

公开(公告)日：2021-03-04

申请号：US16560647

申请日：2019-09-04

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Brandon C. MARIN ,  Jeremy ECTON ,  Hiroki TANAKA ,  Frank TRUONG

IPC: H01L49/02 ,  H01G4/008 ,  H01G4/12 ,  H01L21/48 ,  H01G4/28

Abstract: Embodiments herein relate to a capacitor device or a manufacturing process flow for creating a capacitor that includes nanoislands within a package. The capacitor a first conductive plate having a first side and a second side opposite the first side and a second conductive plate having a first side and a second side opposite the first side where the first side of the first conductive plate faces the first side of the second conductive plate. A first plurality of nanoislands is distributed on the first side of the first conductive plate and a second plurality of nanoislands is distributed on the first side of the second conductive plate, where the first conductive plate, the second conductive plate, and the first and second pluralities of nanoislands form a capacitor. The nanoislands may be applied to the conductive plates using a sputtering technique.

公开(公告)号：US20210050289A1

公开(公告)日：2021-02-18

申请号：US16539254

申请日：2019-08-13

Applicant: Intel Corporation

Inventor： Jieying KONG ,  Srinivas PIETAMBARAM ,  Gang DUAN

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/64

Abstract: Embodiments disclosed herein include hybrid cores for electronic packaging applications. In an embodiment, a package substrate comprises a plurality of glass layers and a plurality of dielectric layers. In an embodiment, the glass layers alternate with the dielectric layers. In an embodiment, a through-hole through the plurality of glass layers and the plurality of dielectric layers is provided. In an embodiment a conductive through-hole via is disposed in the through-hole.

公开(公告)号：US20210014972A1

公开(公告)日：2021-01-14

申请号：US16505403

申请日：2019-07-08

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Tarek IBRAHIM ,  Srinivas PIETAMBARAM ,  Andrew J. BROWN ,  Gang DUAN ,  Jeremy ECTON ,  Sheng C. LI

IPC: H05K1/16 ,  H01L23/00 ,  H01F27/40 ,  H05K1/11 ,  H05K3/40 ,  H05K3/28

Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.