公开(公告)号：US20230317583A1

公开(公告)日：2023-10-05

申请号：US17707358

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Rahul N. MANEPALLI ,  Yi YANG ,  Suddhasattwa NAD ,  Benjamin DUONG ,  Marcel WALL

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/18

CPC classification number: H01L23/49822 ,  H01L23/49866 ,  H01L23/49894 ,  H01L21/4857 ,  H05K1/181 ,  H01L24/16

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate with a plurality of first layers, where the first layers comprise an organic material. In an embodiment, a trace is embedded in the package substrate. In an embodiment, a second layer is over the trace, where the second layer comprises silicon, nitrogen, and a catalyst, and where the second layer is chemically bonded to one of the first layers.

公开(公告)号：US20220102261A1

公开(公告)日：2022-03-31

申请号：US17544693

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Mathew J. MANUSHAROW ,  Krishna BHARATH ,  William J. LAMBERT ,  Robert L. SANKMAN ,  Aleksandar ALEKSOV ,  Brandon M. RAWLINGS ,  Feras EID ,  Javier SOTO GONZALEZ ,  Meizi JIAO ,  Suddhasattwa NAD ,  Telesphor KAMGAING

IPC: H01L23/498 ,  H01F17/00 ,  H01F27/40 ,  H01L49/02 ,  H01F27/28 ,  H01F41/04 ,  H01G4/33 ,  H01L21/48 ,  H01L23/66

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

公开(公告)号：US20190393183A1

公开(公告)日：2019-12-26

申请号：US16017393

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Rahul MANEPALLI ,  Marcel WALL

IPC: H01L23/00 ,  H01L23/29 ,  H01L21/48 ,  H01L21/56

Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a self-assembled monolayers (SAM) layer. The package substrate includes a SAM layer on portions of a conductive pad, where the SAM layer includes alight-reflective moieties. The package substrate also includes a via on a surface portion of the conductive pad, and a dielectric on and around the via, the SAM layer, and the conductive pad, where the SAM layer surrounds and contacts a surface of the via. The SAM layer may be an interfacial organic layer. The light-reflective moieties may include a hemicyanine, a cyclic-hemicyanine, an oligothiophene, and/or a conjugated aromatic compound. The SAM layer may include a molecular structure having a first end group of a first monolayer, an intermediate group, a fifth end group of a second monolayer, and one or more of a first and second light-reflective moieties.

公开(公告)号：US20240312888A1

公开(公告)日：2024-09-19

申请号：US18121264

申请日：2023-03-14

Applicant: Intel Corporation

Inventor： Sashi S. KANDANUR ,  Srinivas V. PIETAMBARAM ,  Darko GRUJICIC ,  Brandon C. MARIN ,  Suddhasattwa NAD ,  Benjamin DUONG ,  Gang DUAN ,  Mohammad Mamunur RAHMAN ,  Numair AHMED

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49838

Abstract: Embodiments herein relate to systems, apparatuses, techniques and/or processes for creating a substrate out of a plurality of layers of glass, where the substrate includes one or more vias that extend through each of the plurality of layers of glass. In embodiments, a high aspect ratio via may be constructed through the substrate by electrically coupling the individual vias. Other embodiments may be described and/or claimed.

公开(公告)号：US20240105571A1

公开(公告)日：2024-03-28

申请号：US17954288

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Haobo CHEN ,  Bai NIE ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Jeremy D. ECTON ,  Suddhasattwa NAD

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49894 ,  H01L23/15

Abstract: Embodiments disclosed herein include glass cores and methods of forming glass cores. In an embodiment, a core for an electronic package comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass, In an embodiment, a via opening is provided through the substrate, and a diffusion layer is along the first surface, the second surface, and the via opening.

公开(公告)号：US20240097079A1

公开(公告)日：2024-03-21

申请号：US17949857

申请日：2022-09-21

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Khaled AHMED ,  Srinivas V. PIETAMBARAM ,  Hiroki TANAKA ,  Paul WEST ,  Kristof DARMAWIKARTA ,  Gang DUAN ,  Jeremy D. ECTON ,  Suddhasattwa NAD

IPC: H01L33/48 ,  H01L25/075 ,  H01L33/00 ,  H01L33/32 ,  H01L33/62

CPC classification number: H01L33/486 ,  H01L25/0753 ,  H01L33/0075 ,  H01L33/32 ,  H01L33/62 ,  H01L2933/0066

Abstract: Integrated circuit (IC) packages are disclosed. In some embodiments, an IC package includes a glass substrate, a micro light emitting diode (LED), a semiconductor die, one or more through glass vias (TGVs) and a package substrate. The micro LED is positioned over the glass substrate. The TGVs are integrated into the glass substrate and connect the micro LED to the semiconductor die. The semiconductor die is connected to the package substrate to receive external signals when connected to a motherboard.

公开(公告)号：US20240087971A1

公开(公告)日：2024-03-14

申请号：US17943915

申请日：2022-09-13

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Gang DUAN ,  Srinivas V. PIETAMBARAM ,  Kristof DARMAWIKARTA ,  Jeremy D. ECTON ,  Suddhasattwa NAD ,  Hiroki TANAKA ,  Pooya TADAYON

IPC: H01L23/15 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/15 ,  H01L23/5381 ,  H01L23/5384 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments disclosed herein include interposers and methods of forming interposers. In an embodiment, an interposer comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. In an embodiment, the interposer further comprises a cavity into the first surface of the substrate, a via through the substrate below the cavity, a first pad in the cavity over the via, and a second pad on the second surface of the substrate under the via.

公开(公告)号：US20240063100A1

公开(公告)日：2024-02-22

申请号：US17889229

申请日：2022-08-16

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Mohammad Mamunur RAHMAN ,  Jeremy D. ECTON ,  Gang DUAN ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM ,  Kemal AYGÜN ,  Cemil GEYIK

IPC: H01L23/498

CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L23/49811

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first layer, where the first layer comprises glass, a second layer over the first layer, where the second layer comprises glass, and a third layer over the second layer, where the third layer comprises glass. In an embodiment, a pair of traces are in the second layer, and a first gap is below the pair of traces, where the first gap is in the first layer and the second layer. In an embodiment, a second gap is above the pair of traces, where the second gap is in the second layer and the third layer.

公开(公告)号：US20230420357A1

公开(公告)日：2023-12-28

申请号：US17848624

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Sameer PAITAL

IPC: H01L23/498 ,  H01L21/02 ,  H01L21/48

CPC classification number: H01L23/49894 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L21/0217 ,  H01L21/486 ,  H01L24/16

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to forming an LGA pad on a side of a substrate, with a layer of silicon nitride between the LGA pad and a dielectric layer of the substrate. The LGA pad may have a reduced footprint, or a reduced lateral dimension with respect to a plane of the substrate, as compared to legacy LGA pads to reduce insertion loss by reducing the resulting capacitance between the reduced LGA footprint and metal routings within the substrate. The layer of silicon nitride may provide additional mechanical support for the reduced footprint. Other embodiments may be described and/or claimed.

公开(公告)号：US20230420322A1

公开(公告)日：2023-12-28

申请号：US17848615

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Yi YANG ,  Srinivas V. PIETAMBARAM ,  Suddhasattwa NAD ,  Darko GRUJICIC ,  Marcel WALL

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/495

CPC classification number: H01L23/3142 ,  H01L23/49827 ,  H01L23/49513

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to an organic adhesion promoter layer on the surface of a copper trace to reduce delamination between a dielectric material and the surface of the copper trace, and to facilitate a smooth surface interface between the surface of the copper trace and of a copper feature, such as a copper-filled via, placed on the surface of the copper trace. The smooth surface interface reduces insertion loss and enables routing of higher frequency signals on a package, and does not require roughing of the copper trace in order to adhere to the dielectric material. Other embodiments may be described and/or claimed.