公开(公告)号：US11922557B2

公开(公告)日：2024-03-05

申请号：US17746691

申请日：2022-05-17

Applicant: Intel Corporation

Inventor： Sven Woop ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Carsten Benthin ,  Joshua Barczak ,  Saikat Mandal

IPC: G06T15/06 ,  G06T15/00

CPC classification number: G06T15/06 ,  G06T15/005 ,  G06T2210/21

Abstract: An apparatus and method for merging primitives and coordinating between vertex and ray transformations on a shared transformation unit. For example, one embodiment of a graphics processor comprises: a queue comprising a plurality of entries; ordering circuitry/logic to order triangles front to back within the queue; pairing circuitry/logic to identify triangles in the queue sharing an edge and to merge the triangles sharing an edge to produce merged triangle pairs; and shared transformation circuitry to alternate between performing vertex transformations on vertices of the merged triangle pairs and to performing ray transformations on ray direction/origin data.

公开(公告)号：US20220366634A1

公开(公告)日：2022-11-17

申请号：US17746691

申请日：2022-05-17

Applicant: Intel Corporation

Inventor： Sven Woop ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Carsten Benthin ,  Joshua Barczak ,  Saikat Mandal

IPC: G06T15/06 ,  G06T15/00

Abstract: An apparatus and method for merging primitives and coordinating between vertex and ray transformations on a shared transformation unit. For example, one embodiment of a graphics processor comprises: a queue comprising a plurality of entries; ordering circuitry/logic to order triangles front to back within the queue; pairing circuitry/logic to identify triangles in the queue sharing an edge and to merge the triangles sharing an edge to produce merged triangle pairs; and shared transformation circuitry to alternate between performing vertex transformations on vertices of the merged triangle pairs and to performing ray transformations on ray direction/origin data.

公开(公告)号：US11341709B2

公开(公告)日：2022-05-24

申请号：US16585880

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Sven Woop ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Carsten Benthin ,  Joshua Barczak ,  Saikat Mandal

IPC: G06T15/06 ,  G06T15/00

Abstract: An apparatus and method for merging primitives and coordinating between vertex and ray transformations on a shared transformation unit. For example, one embodiment of a graphics processor comprises: a queue comprising a plurality of entries; ordering circuitry/logic to order triangles front to back within the queue; pairing circuitry/logic to identify triangles in the queue sharing an edge and to merge the triangles sharing an edge to produce merged triangle pairs; and shared transformation circuitry to alternate between performing vertex transformations on vertices of the merged triangle pairs and to performing ray transformations on ray direction/origin data.

公开(公告)号：US20220068009A1

公开(公告)日：2022-03-03

申请号：US17473770

申请日：2021-09-13

Applicant: INTEL CORPORATION

Inventor： Ingo Wald ,  Carsten Benthin ,  Sven Woop

IPC: G06T15/06 ,  G06T7/50 ,  G06T15/00 ,  G06T15/50

Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.

公开(公告)号：US10719974B1

公开(公告)日：2020-07-21

申请号：US16367062

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Sven Woop ,  Carsten Benthin

IPC: G06T15/06 ,  G06T17/00 ,  G06T9/40 ,  G06T1/60

Abstract: Apparatus and method for preventing re-traversal of a prior path on a restart. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes, wherein the BVH comprises a specified number of child nodes at a current BVH level beneath a parent node in the hierarchy; traversal/intersection circuitry to traverse one or more of the rays through the hierarchically arranged nodes of the BVH to form a current traversal path and intersect the one or more rays with primitives contained within the nodes; and traversal tracking circuitry to maintain a path encoding array to store path data related to the current traversal path, the path data comprising an index of a currently traversed child node; wherein the traversal/intersection circuitry is to prevent one or more subsequent rays from re-intersecting primitives from which they originated and/or avoid re-traversing the current traversal path based on the path data in the path encoding array.

公开(公告)号：US09928640B2

公开(公告)日：2018-03-27

申请号：US14975294

申请日：2015-12-18

Applicant: INTEL CORPORATION

Inventor： Sven Woop ,  Carsten Benthin ,  Rasmus Barringer ,  Tomas G. Akenine-Moller

IPC: G06T15/00 ,  G06T15/06 ,  G06T15/08

CPC classification number: G06T15/06 ,  G06T15/005 ,  G06T15/08 ,  G06T2210/08 ,  G06T2210/12

Abstract: Embodiments provide for a graphics processing apparatus including a graphics processing unit having bounding volume logic to operate on a compressed bounding volume hierarchy, wherein each bounding volume node stores a parent bounding volume and multiple child bounding volumes that are encoded relative to the parent bounding volume.

公开(公告)号：US12223585B2

公开(公告)日：2025-02-11

申请号：US18376098

申请日：2023-10-03

Applicant: INTEL CORPORATION

Inventor： Karol Szerszen ,  Prasoonkumar Surti ,  Gabor Liktor ,  Karthik Vaidyanathan ,  Sven Woop

IPC: G06T15/00 ,  G06T1/20 ,  G06T15/06 ,  G06T15/08 ,  G06T17/10

Abstract: Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.

公开(公告)号：US11783530B2

公开(公告)日：2023-10-10

申请号：US17677109

申请日：2022-02-22

Applicant: INTEL CORPORATION

Inventor： Karol Szerszen ,  Prasoonkumar Surti ,  Gabor Liktor ,  Karthik Vaidyanathan ,  Sven Woop

IPC: G06T15/00 ,  G06T15/06 ,  G06T15/08 ,  G06T1/20 ,  G06T17/10

CPC classification number: G06T15/06 ,  G06T1/20 ,  G06T15/005 ,  G06T15/08 ,  G06T17/10

Abstract: Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.

公开(公告)号：US20230298126A1

公开(公告)日：2023-09-21

申请号：US17699059

申请日：2022-03-18

Applicant: INTEL CORPORATION

Inventor： Sven Woop ,  Carsten Benthin ,  Prasoonkumar Surti ,  Joshua Barczak ,  Abhishek R. Appu ,  Pawel Majewski

IPC: G06T1/60 ,  G06T1/20 ,  G06T15/10 ,  G06T15/06 ,  G06F12/0862 ,  G06F12/0811

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T15/10 ,  G06T15/06 ,  G06F12/0862 ,  G06F12/0811

Abstract: Apparatus and method for prefetching node data. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to manage active ray tracing stack allocations within a traversal stack; and stack management hardware logic to issue a prefetch operation comprising an indication of bounding volume hierarchy (BVH) node data to be prefetched and an indication of a cache level, wherein responsive to performing the prefetch operation, the BVH node data is to be prefetched to the indicated cache level.

公开(公告)号：US11721059B2

公开(公告)日：2023-08-08

申请号：US17473770

申请日：2021-09-13

Applicant: INTEL CORPORATION

Inventor： Ingo Wald ,  Carsten Benthin ,  Sven Woop

IPC: G06T15/06 ,  G06T7/50 ,  G06T15/00 ,  G06T15/50 ,  G06T1/20

CPC classification number: G06T15/06 ,  G06T7/50 ,  G06T15/005 ,  G06T15/506 ,  G06T1/20 ,  G06T2210/21

Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.