公开(公告)号：US20240394956A1

公开(公告)日：2024-11-28

申请号：US18675746

申请日：2024-05-28

Applicant: Intel Corporation

Inventor： Sven Woop ,  Michael J. Doyle ,  Sreenivas Kothandaraman ,  Karthik Vaidyanathan ,  Abhishek R. Appu ,  Carsten Benthin ,  Prasoonkumar Surti ,  Holger Gruen ,  Stephen Junkins ,  Adam Lake ,  Bret G. Alfieri ,  Gabor Liktor ,  Joshua Barczak ,  Won-Jong Lee

IPC: G06T15/06 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: Apparatus and method for efficient graphics processing including ray tracing. For example, one embodiment of a graphics processor comprises: execution hardware logic to execute graphics commands and render images; an interface to couple functional units of the execution hardware logic to a tiled resource; and a tiled resource manager to manage access by the functional units to the tiled resource, a functional unit of the execution hardware logic to generate a request with a hash identifier (ID) to request access to a portion of the tiled resource, wherein the tiled resource manager is to determine whether a portion of the tiled resource identified by the hash ID exists, and if not, to allocate a new portion of the tiled resource and associate the new portion with the hash ID.

公开(公告)号：US11657472B2

公开(公告)日：2023-05-23

申请号：US17707118

申请日：2022-03-29

Applicant: INTEL CORPORATION

Inventor： Carsten Benthin ,  Sven Woop ,  Ingo Wald

IPC: G06T15/00 ,  G06T1/20 ,  G06F9/38 ,  G06T15/06 ,  G06T17/10

CPC classification number: G06T1/20 ,  G06F9/3877 ,  G06T15/005 ,  G06T15/06 ,  G06T17/10 ,  G06T2210/12

Abstract: Apparatus and method for compressing an acceleration data structure such as a bounding volume hierarchy (BVH). For example, one embodiment of a graphics processing apparatus comprises: one or more cores to execute graphics instructions including instructions to perform ray tracing operations; and compression circuitry to compress lowest level nodes of a hierarchical acceleration data structure comprising a plurality of hierarchically arranged nodes, each of the lowest level nodes comprising pointers to leaf data; the compression circuitry to quantize the lowest level nodes to generate quantized lowest level nodes and to store each quantized lowest level node and associated leaf data without the pointers to the leaf data.

公开(公告)号：US11315304B2

公开(公告)日：2022-04-26

申请号：US17003011

申请日：2020-08-26

Applicant: INTEL CORPORATION

Inventor： Scott Janus ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Alexey Supikov ,  Gabor Liktor ,  Carsten Benthin ,  Philip Laws ,  Michael Doyle

IPC: G06T15/06 ,  G06T17/00 ,  G06T1/60 ,  G06T15/00

Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.

公开(公告)号：US11189076B2

公开(公告)日：2021-11-30

申请号：US16929671

申请日：2020-07-15

Applicant: INTEL CORPORATION

Inventor： Karthik Vaidyanathan ,  Sven Woop ,  Carsten Benthin

IPC: G06T15/06 ,  G06T1/60 ,  G06T9/40 ,  G06T17/00

Abstract: Apparatus and method for preventing re-traversal of a prior path on a restart. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a graphics scene; a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes, wherein the BVH comprises a specified number of child nodes at a current BVH level beneath a parent node in the hierarchy; circuitry to traverse one or more of the rays through the BVH to form a current traversal path and intersect the one or more rays with primitives contained within the nodes, wherein the circuitry is to process entries from the top of a first data structure comprising entries each associated with a child node at the current BVH level, the entries being ordered from top to bottom based on a sorted distance of each respective child node.

公开(公告)号：US10957095B2

公开(公告)日：2021-03-23

申请号：US16056222

申请日：2018-08-06

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Won-Jong Lee ,  Gabor Liktor ,  John G. Gierach ,  Pawel Majewski ,  Prasoonkumar Surti ,  Carsten Benthin ,  Sven Woop ,  Thomas Raoux

IPC: G06T15/00 ,  G06T15/06 ,  G06T15/80 ,  G06T1/60 ,  G09G5/36

Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.

公开(公告)号：US10600231B2

公开(公告)日：2020-03-24

申请号：US15924112

申请日：2018-03-16

Applicant: Intel Corporation

Inventor： Sven Woop ,  Carsten Benthin ,  Rasmus Barringer ,  Tomas G. Akenine-Moller

IPC: G06T15/00 ,  G06T15/06 ,  G06T15/08

Abstract: Embodiments provide for a graphics processing apparatus including a graphics processing unit having bounding volume logic to operate on a compressed bounding volume hierarchy, wherein each bounding volume node stores a parent bounding volume and multiple child bounding volumes that are encoded relative to the parent bounding volume.

公开(公告)号：US12229871B2

公开(公告)日：2025-02-18

申请号：US17481656

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Atsuo Kuwahara ,  Hugues Labbe ,  Sameer K P ,  Jonathan Kennedy ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Tomer Bar-On ,  Carsten Benthin ,  Adam T. Lake ,  Vasanth Ranganathan ,  Abhishek R. Appu

IPC: G06T15/08 ,  G02B27/01 ,  G06T15/00 ,  G06T15/10 ,  G06T15/60 ,  G06V20/40 ,  G06V40/19 ,  H04N13/239 ,  H04N13/344 ,  H04N23/67 ,  H04N25/702

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

公开(公告)号：US11776196B2

公开(公告)日：2023-10-03

申请号：US17868610

申请日：2022-07-19

Applicant: INTEL CORPORATION

Inventor： Sven Woop ,  Attila Afra ,  Carsten Benthin ,  Ingo Wald ,  Johannes Guenther

IPC: G06T15/00 ,  G06T15/06 ,  G06T1/20 ,  G06T17/00

CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T15/06 ,  G06T17/00 ,  G09G2360/00

Abstract: A graphics processing apparatus comprising bounding volume hierarchy (BVH) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a BVH comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the BVH in accordance with the spatial and temporal components.

公开(公告)号：US11367243B2

公开(公告)日：2022-06-21

申请号：US17108774

申请日：2020-12-01

Applicant: Intel Corporation

Inventor： Carsten Benthin ,  Ingo Wald ,  Gabor Liktor ,  Johannes Guenther ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06T15/06 ,  G06T15/00 ,  G06T9/00 ,  G06T9/40

Abstract: An apparatus and method for performing BVH compression and decompression concurrently with stores and loads, respectively. For example, one embodiment comprises: bounding volume hierarchy (BVH) construction circuitry to build a BVH based on a set of input primitives, the BVH comprising a plurality of uncompressed coordinates; traversal/intersection circuitry to traverse one or more rays through the BVH and determine intersections with the set of input primitives using the uncompressed coordinates; store with compression circuitry to compress the BVH including the plurality of uncompressed coordinates to generate a compressed BVH with compressed coordinates and to store the compressed BVH to a memory subsystem; and load with decompression circuitry to decompress the BVH including the compressed coordinates to generate a decompressed BVH with the uncompressed coordinates and to load the decompressed BVH with uncompressed coordinates to a cache and/or a set of registers accessible by the traversal/intersection circuitry.

公开(公告)号：US11189074B2

公开(公告)日：2021-11-30

申请号：US16890254

申请日：2020-06-02

Applicant: INTEL CORPORATION

Inventor： Carsten Benthin ,  Sven Woop

IPC: G06T15/06 ,  G06T17/00

Abstract: An apparatus and method for efficiently reconstructing a BVH. For example, one embodiment of a method comprises: constructing an object bounding volume hierarchy (BVH) for each object in a scene, each object BVH including a root node and one or more child nodes based on primitives included in each object; constructing a top-level BVH using the root nodes of the individual object BVHs; performing an analysis of the top-level BVH to determine whether the top-level BVH comprises a sufficiently efficient arrangement of nodes within its hierarchy; and reconstructing at least a portion of the top-level BVH if a more efficient arrangement of nodes exists, wherein reconstructing comprises rebuilding the portion of the top-level BVH until one or more stopping criteria have been met, the stopping criteria defined to prevent an entire rebuilding of the top-level BVH.