公开(公告)号：US20230197646A1

公开(公告)日：2023-06-22

申请号：US17557948

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Telesphor KAMGAING ,  Georgios C. DOGIAMIS ,  Neelam PRABHU GAUNKAR ,  Veronica STRONG ,  Brandon RAWLINGS ,  Andrew P. COLLINS ,  Arghya SAIN ,  Sivaseetharaman PANDI

IPC: H01L23/66 ,  H01L23/15 ,  H01L23/498 ,  H01P3/08

CPC classification number: H01L23/66 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49838 ,  H01P3/081 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6638

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. In an embodiment, the electronic package further comprises a trace embedded in the substrate, where a width of the trace is less than a height of the trace. In an embodiment, the electronic package further comprises a first layer on the first surface of the substrate, where the first layer is a dielectric buildup film, and a second layer on the second surface of the substrate, where the second layer is the dielectric buildup film.

公开(公告)号：US20220416391A1

公开(公告)日：2022-12-29

申请号：US17356023

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Georgios C. DOGIAMIS ,  Neelam PRABHU GAUNKAR ,  Veronica STRONG ,  Aleksandar ALEKSOV

IPC: H01P3/00 ,  H01L23/15 ,  H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H01P11/00

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to positioning signal and ground vias, or ground planes, in a glass core to control impedance within a package. Laser-assisted etching processes may be used to create vertical controlled impedance lines to enhance bandwidth and bandwidth density of high-speed signals on a package. Other embodiments may be described and/or claimed.

公开(公告)号：US20220415779A1

公开(公告)日：2022-12-29

申请号：US17357896

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Georgios C. DOGIAMIS ,  Aleksandar ALEKSOV ,  Veronica STRONG ,  Neelam PRABHU GAUNKAR ,  Telesphor KAMGAING

IPC: H01L23/498 ,  H01L23/15 ,  H01L21/48

Abstract: Embodiments disclosed herein include package substrates with angled vias and/or via planes. In an embodiment, a package substrate comprises a core with a first surface and a second surface opposite from the first surface. In an embodiment, a first pad is on the first surface, and a second pad on the second surface, where the second pad is outside a footprint of the first pad. In an embodiment, the package substrate further comprises a via through a thickness of the core, where the via connects the first pad to the second pad.

公开(公告)号：US20220406725A1

公开(公告)日：2022-12-22

申请号：US17350175

申请日：2021-06-17

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Veronica STRONG ,  Neelam PRABHU GAUNKAR ,  Georgios C. DOGIAMIS ,  Aleksandar ALEKSOV ,  Johanna M. SWAN

IPC: H01L23/552 ,  H01L23/15 ,  H01L23/498 ,  H01L21/48

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to glass interposers or substrates that may be created using a glass etching process to enable highly integrated modules. Planar structures, which may be vertical planar structures, created within the glass interposer may be used to provide shielding for conductive vias in the glass interposer, to increase the signal density within the glass substrate and to reduce cross talk. Other embodiments may be described and/or claimed.

公开(公告)号：US20220406686A1

公开(公告)日：2022-12-22

申请号：US17349695

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Telesphor KAMGAING ,  Neelam PRABHU GAUNKAR ,  Georgios C. DOGIAMIS ,  Veronica STRONG

IPC: H01L23/473 ,  H01L23/13 ,  H01L23/15 ,  H01L23/467 ,  H01L23/498 ,  H01L21/48

Abstract: Embodiments disclosed herein include package substrates and methods of forming such package substrates. In an embodiment a package substrate comprises a core with a first surface and a second surface opposite from the first surface. In an embodiment, a buildup layer is over the first surface of the core. In an embodiment, a channel is through the core, where the channel extends in a direction that is substantially parallel to the first surface.

公开(公告)号：US20220406616A1

公开(公告)日：2022-12-22

申请号：US17349667

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Veronica STRONG ,  Aleksandar ALEKSOV ,  Georgios C. DOGIAMIS ,  Telesphor KAMGAING ,  Neelam PRABHU GAUNKAR

IPC: H01L21/48 ,  H01L23/498

Abstract: Embodiments disclosed herein include package substrates and methods of fabricating such substrates. In an embodiment, a package substrate comprises a core with a first surface and a second surface opposite from the first surface. The package substrate further comprises a via hole through the core. In an embodiment the via hole comprises a first portion, a second portion, and a perforated ledge between the first portion and the second portion. In an embodiment, the package substrate further comprises a via filling the via hole.

公开(公告)号：US20220404568A1

公开(公告)日：2022-12-22

申请号：US17350809

申请日：2021-06-17

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Telesphor KAMGAING ,  Veronica STRONG ,  Neelam PRABHU GAUNKAR ,  Georgios C. DOGIAMIS

IPC: G02B6/42

Abstract: Embodiments disclosed herein include electronic packages with a core that includes an optical waveguide and methods of forming such electronic packages. In an embodiment, a package substrate comprises a core, and a photonics die embedded in the core. In an embodiment, the electronic package further comprises an optical waveguide embedded in the core. In an embodiment, the optical waveguide optically couples the photonics die to an edge of the core.

公开(公告)号：US20200294901A1

公开(公告)日：2020-09-17

申请号：US16649578

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Veronica STRONG ,  Aleksandar ALEKSOV ,  Brandon RAWLINGS ,  Johanna SWAN

IPC: H01L23/498 ,  H01L23/48 ,  H01L23/538 ,  H01L21/48

Abstract: Device package and a method of forming a device package are described. The device package includes an interposer with interconnects on an interconnect package layer and a conductive layer on the interposer. The device package has dies on the conductive layer, where the package layer includes a zero-misalignment two-via stack (ZM2VS) and a dielectric. The ZM2VS directly coupled to the interconnect. The ZM2VS further includes the dielectric on a conductive pad, a first via on a first seed, and first seed on a top surface of the conductive pad, where the first via extends through dielectric. The ZM2VS also has a conductive trace on dielectric, and a second via on a second seed, the second seed is on the dielectric, where the conductive trace connects to first and second vias, where second via connects to an edge of conductive trace opposite from first via.

公开(公告)号：US20200258839A1

公开(公告)日：2020-08-13

申请号：US16648850

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Veronica STRONG ,  Brandon RAWLINGS

IPC: H01L23/538 ,  H01L23/498

Abstract: A device package and a method of forming a device package are described. The device package includes a dielectric on a conductive pad, and a first via on a first seed on a top surface of the conductive pad. The device package further includes a conductive trace on the dielectric, and a second via on a second seed layer on the dielectric. The conductive trace connects to the first via and the second via, where the second via connects to an edge of the conductive trace opposite from the first via. The dielectric may include a photoimageable dielectric or a buildup film. The device package may also include a seed on the dielectric prior to the conductive trace on the dielectric, and a second dielectric on the dielectric, the conductive trace, and the first and second vias, where the second dielectric exposes a top surface of the second via.