公开(公告)号：DE69428181D1

公开(公告)日：2001-10-11

申请号：DE69428181

申请日：1994-12-09

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： TOMURA YOSHIHIRO ,  BESSHO YOSHIHIRO ,  HAKOTANI YASUHIKO

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/485 ,  H01L23/498 ,  H05K1/18 ,  H05K3/24 ,  H05K3/32 ,  H05K3/40

Abstract: A chip carrier according to the present invention includes: a carrier body including an upper face, a lower face, and an internal conductor; and a plurality of terminal electrodes formed on the upper face of the carrier body, the plurality of terminal electrodes electrically connecting an LSI chip to the internal conductor. A plurality of concave portions for electrically connecting a plurality of electrodes on a circuit substrate to the internal conductor are provided on the lower face of the carrier body, the concave portions being electrically connected to the internal conductor.

公开(公告)号：AU1053499A

公开(公告)日：1999-06-07

申请号：AU1053499

申请日：1998-11-13

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： TAKEZAWA HIROAKI ,  TSUKAMOTO MASAHIDE ,  ITAGAKI MINEHIRO ,  BESSHO YOSHIHIRO ,  HATANAKA HIDEO ,  FUKUMURA YASUSHI ,  EDA KAZUO ,  ISHIDA TORU

IPC: H01L23/12 ,  H01L21/60 ,  H01L23/32 ,  H01L23/498 ,  H05K1/02 ,  H05K3/10 ,  H05K3/32 ,  H05K3/34 ,  H01L21/768

Abstract: A stress relaxation type electronic component which is to be mounted on a circuit board, wherein a stress relaxation mechanism member is disposed on a surface of said electronic component, said surface being on a side of a connection portion where said electronic component is to be connected to said circuit board, and said stress relaxation mechanism member is electrically conductive.

公开(公告)号：CA2310765C

公开(公告)日：2005-07-12

申请号：CA2310765

申请日：1998-11-13

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： TAKEZAWA HIROAKI ,  TSUKAMOTO MASAHIDE ,  BESSHO YOSHIHIRO ,  ITAGAKI MINEHIRO ,  FUKUMURA YASUSHI ,  HATANAKA HIDEO ,  ISHIDA TORU ,  EDA KAZUO

IPC: H01L23/12 ,  H01L21/60 ,  H01L23/32 ,  H01L23/498 ,  H05K1/02 ,  H05K3/10 ,  H05K3/32 ,  H05K3/34 ,  H01L21/768

Abstract: A stress relaxation type electronic component which is to be mounted on a circuit board, wherein a stress relaxation mechanism member is disposed on a surface of said electronic component, said surface being on a side of a connection portion where said electronic component is to be connected to said circuit board, and said stress relaxation mechanism member is electrically conductive.

公开(公告)号：DE69628767T2

公开(公告)日：2004-02-12

申请号：DE69628767

申请日：1996-01-30

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： OMOYA KAZUNORI ,  OOBAYASHI TAKASHI ,  SAKURAI WATARU ,  HARADA MITSURU ,  BESSHO YOSHIHIRO

IPC: H01L21/56 ,  H01L21/60 ,  H01L23/29 ,  H01L23/485

Abstract: An improved semiconductor unit package method is disclosed. This method is implemented by a semiconductor device having an electrode pad, a substrate having a terminal electrode, a bump electrode formed on the electrode pad, a conductive adhesion layer with flexibility, and an encapsulating layer formed by curing a composition the viscosity and thixotropy index of which are below 100 Pa . s and below 1.1, respectively. Such a composition essentially consists of (A) a resin binder that contains, for example, a polyepoxide, an acid anhydride, and a rheology modifier and (B) a filler. The rheology modifier is one capable of impeding interaction between a free acid contained in the acid anhydride and a polar group at the surface of the filler. An encapsulant with improved flowability is used, so that the encapsulant readily flows and spreads to fill a gap between the semiconductor device and the substrate with no air bubbles. This achieves semiconductor unit packages with high reliability and productivity.

公开(公告)号：DE69628767D1

公开(公告)日：2003-07-24

申请号：DE69628767

申请日：1996-01-30

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： OMOYA KAZUNORI ,  OOBAYASHI TAKASHI ,  SAKURAI WATARU ,  HARADA MITSURU ,  BESSHO YOSHIHIRO

IPC: H01L21/56 ,  H01L21/60 ,  H01L23/29 ,  H01L23/485

Abstract: An improved semiconductor unit package method is disclosed. This method is implemented by a semiconductor device having an electrode pad, a substrate having a terminal electrode, a bump electrode formed on the electrode pad, a conductive adhesion layer with flexibility, and an encapsulating layer formed by curing a composition the viscosity and thixotropy index of which are below 100 Pa . s and below 1.1, respectively. Such a composition essentially consists of (A) a resin binder that contains, for example, a polyepoxide, an acid anhydride, and a rheology modifier and (B) a filler. The rheology modifier is one capable of impeding interaction between a free acid contained in the acid anhydride and a polar group at the surface of the filler. An encapsulant with improved flowability is used, so that the encapsulant readily flows and spreads to fill a gap between the semiconductor device and the substrate with no air bubbles. This achieves semiconductor unit packages with high reliability and productivity.

公开(公告)号：DE69430935D1

公开(公告)日：2002-08-14

申请号：DE69430935

申请日：1994-05-10

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： ITAGAKI MINEHIRO ,  BESSHO YOSHIHIRO ,  YUHAKU SATORU ,  HAKOTANI YASUHIKO ,  MIURA KAZUHIRO ,  OKANO KAZUYUKI

IPC: H01B1/16 ,  H01L21/48 ,  C04B41/88 ,  H01L23/498 ,  H05K1/09 ,  H05K3/46

Abstract: A conductive paste includes inorganic material powders containing conductive powders and glass powders, an organic vehicle containing an organic binder and an organic solvent, and a metal organic compound.

公开(公告)号：DE69329357T2

公开(公告)日：2001-04-26

申请号：DE69329357

申请日：1993-04-30

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： ITAGAKI MINEHIRO ,  OKANO KAZUYUKI ,  KIMURA SUZUSHI ,  NAKATANI SEIICHI ,  BESSHO YOSHIHIRO ,  YUHAKU SATORU ,  HAKOTANI YASUHIKO ,  MIURA KAZUHIRO

IPC: H01L23/498 ,  H01L21/48

Abstract: Conductive paste for via connection (6) of a multilayer ceramic substrate (K), comprising: an inorganic component which consists of 30.0 to 70.0 % by weight of powder of conductive material and the remainder being one of glass powder having a softening point higher than a starting point of sintering of insulating material and crystalline glass ceramic powder having a glass transition point higher than the starting point of sintering of the insulating material; and an organic vehicle component which consists of at least organic binder and solvent.

公开(公告)号：DE69426347D1

公开(公告)日：2001-01-04

申请号：DE69426347

申请日：1994-09-27

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： BESSHO YOSHIHIRO ,  TOMURA YOSHIHIRO

IPC: H01L21/56 ,  H01L23/485 ,  H01L21/60 ,  H01L21/58 ,  H01L23/532

公开(公告)号：CA2310765A1

公开(公告)日：1999-05-27

申请号：CA2310765

申请日：1998-11-13

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： HATANAKA HIDEO ,  FUKUMURA YASUSHI ,  TAKEZAWA HIROAKI ,  ISHIDA TORU ,  TSUKAMOTO MASAHIDE ,  BESSHO YOSHIHIRO ,  EDA KAZUO ,  ITAGAKI MINEHIRO

IPC: H01L23/12 ,  H01L21/60 ,  H01L23/32 ,  H01L23/498 ,  H05K1/02 ,  H05K3/10 ,  H05K3/32 ,  H05K3/34 ,  H01L21/768

Abstract: A stress relaxation electronic part to be mounted on a wiring board and having a conductive stress relaxing mechanism body on the side where the part is connected to the wiring board.

公开(公告)号：DE69415371D1

公开(公告)日：1999-02-04

申请号：DE69415371

申请日：1994-01-28

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： TOMURA YOSHIHIRO ,  BESSHO YOSHIHIRO

IPC: H01L21/60

Abstract: According to the present invention, a method for forming bumps for electrically connecting electrode pads of a semiconductor device to terminal electrodes formed on a surface of a circuit board respectively, the semiconductor device being mounted facedown on the surface of the circuit board, includes: step a of forming the bumps on the electrode pad of the semiconductor device; step b of placing facedown the semiconductor device on a flat foundation so that the bumps contact with a grind sheet which is fixed to the flat foundation and which has abrasive grind; and step c of conducting ultrasonic vibration on the flat foundation while pressing the semiconductor device against the flat foundation, thereby forming a rugged side in a front end portion of each of the bumps.