公开(公告)号：US6372548B2

公开(公告)日：2002-04-16

申请号：US32639899

申请日：1999-06-04

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： BESSHO YOSHIHIRO ,  ITAGAKI MINEHIRO

IPC: H01L21/56 ,  H01L21/60 ,  H01L23/498 ,  H01L21/603

CPC classification number: H01L24/83 ,  H01L21/563 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

Abstract: A semiconductor device has (a) a semiconductor component; (b) a circuit substrate; (c) a base material which is placed between the semiconductor component and the circuit substrate; and (d) a conductive paste, which is filled into a hole formed in the base material, for electrically connecting between a terminal electrode of the semiconductor component and an internal connection electrode of the circuit substrate.

Abstract translation: 半导体器件具有（a）半导体元件; （b）电路基板; （c）放置在半导体部件和电路基板之间的基材; 和（d）填充到形成在基材中的孔中的导电膏，用于电连接半导体部件的端子电极和电路基板的内部连接电极。

公开(公告)号：US6372547B2

公开(公告)日：2002-04-16

申请号：US3806998

申请日：1998-03-11

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： NAKAMURA YOSHIFUMI ,  BESSHO YOSHIHIRO ,  ITAGAKI MINEHIRO

IPC: H01L23/12 ,  H01L21/60 ,  H01L23/498 ,  H05K3/28 ,  H05K3/30 ,  H05K3/34 ,  H01L21/48

CPC classification number: H01L24/81 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17104 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/351 ,  H05K3/284 ,  H05K3/305 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/0129 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/043 ,  H05K2203/1105 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In BGA (Ball Grid Array), LGA (Land Grid Array) and the like, a resin layer is formed between an external connecting electrode of a chip carrier and a circuit wiring board. Consequently, the external connecting electrode can be prevented from cracking due to a difference between the coefficients of thermal expansion of the external connecting electrode and the circuit wiring board. Thus, the reliability in a thermal shock test can be enhanced. A connecting wiring which is conducted to an electrode of a semiconductor device is provided on a surface of an electrical insulating board, and the external connecting electrode for connection to a connecting electrode of the circuit wiring board is provided on a back face of the electrical insulating board. The external connecting electrode has a solder ball made of a conductor, and the resin layer formed on the side portion thereof.

Abstract translation: 在BGA（球栅阵列），LGA（Land Grid Array）等中，在芯片载体的外部连接电极和电路布线基板之间形成树脂层。 因此，可以防止外部连接电极由于外部连接电极和电路布线板的热膨胀系数之间的差而破裂。 因此，可以提高热冲击试验的可靠性。 导电到半导体器件的电极的连接布线设置在电绝缘板的表面上，并且用于连接到电路布线板的连接电极的外部连接电极设置在电绝缘层的背面 板。 外部连接电极具有由导体制成的焊球，树脂层形成在其侧部。

公开(公告)号：EP0721209A3

公开(公告)日：1998-09-09

申请号：EP96100080

申请日：1996-01-04

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： TOMURA YOSHIHIRO ,  BESSHO YOSHIHIRO ,  NAKAMURA YOSHIFUMI

IPC: H01L21/60 ,  G01R1/073 ,  G01R31/26 ,  G01R31/28 ,  H01L21/66 ,  H01L23/12 ,  H01R4/04

CPC classification number: H01R4/04 ,  G01R1/07314 ,  G01R31/2886 ,  H01L22/20 ,  H01L2224/1134 ,  H01L2224/11822 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: Conductive adhesive for checking electric circuits is formed on contact electrodes (8,9) of a chip package or a multi-chip module. After contact electrodes (8,9) of the chip package or the multi-chip module are set on terminal electrodes (18) of a checking device in a correct position, the chip package or the multi-chip module is mounted on the checking device, so that the contact electrodes (8,9) are electrically connected to the terminal electrodes (18) with the conductive adhesive (17) in-between, and thus the electric circuits of the chip package or the multi-chip module are checked.

公开(公告)号：EP1156707A4

公开(公告)日：2006-12-20

申请号：EP00977895

申请日：2000-11-24

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： SUZUKI TAKESHI ,  OGAWA TATSUO ,  TOMEKAWA SATORU ,  BESSHO YOSHIHIRO ,  NISHIYAMA TOUSAKU ,  OGURA TETSUYOSHI

IPC: H05K1/03 ,  H05K3/20 ,  H05K3/40 ,  H05K3/46 ,  H05K1/11

CPC classification number: H05K3/462 ,  H05K1/0373 ,  H05K3/20 ,  H05K3/4069 ,  H05K3/4652 ,  H05K3/4658 ,  H05K2201/0116 ,  H05K2201/0212 ,  H05K2201/0355 ,  H05K2201/10378 ,  H05K2203/1461 ,  Y10T29/49165

Abstract: A wiring board having a high reliability in the insulation and connection of wiring layers, and a production method thereof, the wiring board comprising wiring layers (407) consisting of at least two layers, insulation layers (402) interposed between wiring layers and containing organic resin, and vias (507) provided in insulation layers and extending up to the wiring layers, wherein vias contain functional matters (403) and clearances (404) with part of the clearances (first clearances) having organic resin seeped thereinto from insulation layers and the remaining clearances (second clearances) still filled with air, whereby the flowing of conductive paste into insulation layers, or so called paste bleeding, is eliminated, the second clearances in vias act to lower or soften the modulus of elasticity of the vias as a whole, and a stretching follow-up in response to a mechanical stress on the wiring board is improved to prevent the both wiring layers from being wire-broken to thereby ensure high reliability in electrical and mechanical connections between the both wiring layers.

公开(公告)号：EP0794616A3

公开(公告)日：1998-05-27

申请号：EP97103617

申请日：1997-03-05

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： ONISHI KEJI ,  IWAKI HIDEKI ,  SEKI SHUN-ICHI ,  TAGUCHI YUTAKA ,  SHIRAISHI TSUKASA ,  BESSHO YOSHIHIRO ,  KAWASAKI OSAMU ,  EDA KAZUO

IPC: H03H3/08 ,  H03H9/10

CPC classification number: H03H9/0509 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/45144 ,  H01L2924/00013 ,  H01L2924/09701 ,  H01L2924/16152 ,  H03H3/08 ,  H03H9/0585 ,  H03H9/059 ,  H03H9/1042 ,  H03H9/1071 ,  H03H9/1085 ,  H03H9/1092 ,  Y10T29/42 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: The present invention relates to an electronic part used for mobile communications apparatuses and the like, and more particularly to an electronic part, such as an acoustic surface-wave device, a piezoelectric ceramic device or the like, which requires an oscillation space near the surface of the functional device chip thereof, and a method of production thereof. With this method, a space retainer (5) for forming a sealed space (20) at the functional portion of the chip can be hermetically sealed and have high moisture resistance, and the process of forming the space retainer can be carried out easily.
The electronic part of the present invention comprises a functional device chip (1), a space retainer for forming a sealed space at the functional portion of the chip, a circuit substrate (8) to which the chip is secured, electrode interconnection portions (6) for establishing electric connection between the chip and the circuit substrate, and a sealing resin (7) for covering and sealing at least the space retainer, wherein the space retainer comprises a support layer (52) made of a synthetic resin film, provided with an opening enclosing the functional portion and joined onto the main surface, and a cover (56) formed and joined onto the support layer so as to cover the functional portion and form a sealed space between the cover and the functional portion.

Abstract translation: 用于移动通信设备等的电子部件技术领域本发明涉及用于移动通信设备等的电子部件，更具体地涉及在表面附近需要振荡空间的诸如声表面波器件，压电陶瓷器件等的电子部件 其功能器件芯片及其制造方法。 利用该方法，用于在芯片的功能部分处形成密封空间（20）的空间保持器（5）可以被气密地密封并且具有高防潮性，并且可以容易地执行形成空间保持器的过程。 本发明的电子部件包括功能器件芯片（1），用于在芯片的功能部分形成密封空间的空间保持器，固定芯片的电路衬底（8），电极互连部分（6 ），用于在所述芯片和所述电路基板之间建立电连接;以及密封树脂（7），用于至少覆盖和密封所述空间保持器，其中所述空间保持器包括由合成树脂膜制成的支撑层（52），所述支撑层 包围功能部并接合到主表面上的开口以及形成并接合到支撑层上以覆盖功能部并在盖和功能部之间形成密封空间的盖（56）。

公开(公告)号：EP1041616A4

公开(公告)日：2005-05-11

申请号：EP98953052

申请日：1998-11-13

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： TAKEZAWA HIROAKI ,  TSUKAMOTO MASAHIDE ,  ITAGAKI MINEHIRO ,  BESSHO YOSHIHIRO ,  HATANAKA HIDEO ,  FUKUMURA YASUSHI ,  EDA KAZUO ,  ISHIDA TORU

IPC: H01L23/12 ,  H01L21/60 ,  H01L23/32 ,  H01L23/498 ,  H05K1/02 ,  H05K3/10 ,  H05K3/32 ,  H05K3/34 ,  H01L21/768

CPC classification number: H05K3/3436 ,  H01L23/49816 ,  H01L2224/16225 ,  H05K1/0271 ,  H05K3/105 ,  H05K3/321 ,  H05K2201/0212 ,  H05K2201/0379 ,  H05K2201/10257 ,  H05K2201/10992 ,  H05K2203/121 ,  Y02P70/613 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/254 ,  Y10T428/31681

Abstract: A stress relaxation electronic part to be mounted on a wiring board and having a conductive stress relaxing mechanism body on the side where the part is connected to the wiring board.

公开(公告)号：EP1189272A4

公开(公告)日：2005-03-02

申请号：EP01912364

申请日：2001-03-14

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： NAKATANI SEIICHI ,  BESSHO YOSHIHIRO ,  SUGAYA YASUHIRO ,  ONISHI KEIJI

IPC: H01L21/56 ,  H01L21/68 ,  H01L23/31 ,  H05K1/18 ,  H01L23/28 ,  H01L25/065

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L23/3107 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/45144 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/187 ,  H05K3/20 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/10378 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49146 ,  Y10T29/53174 ,  Y10T29/53178 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05624 ,  H01L2924/00014

Abstract: Two or more electric elements (203), such as semiconductor chip and surface acoustic wave elements, are mounted on a wiring pattern (201), and molded with thermosetting resin (204). ?The upper surface of the electric elements (203) and the upper surface of a thermosetting resin (204) are ground so that their top surfaces may substantially level with each other. The grinding of the molded electric elements (203) can provide a mechanically rigid, thin module with built-in electric elements without causing damage the electric elements (203), while keeping contaminants or abrasives away from the electric elements (203) and the wiring pattern (201).

Abstract translation: 至少两个电子元件（203）如半导体芯片或声表面波器件安装在布线图案（201）上，电气元件（203）用热固性树脂组合物（204）密封。 所述至少两个电气元件（203）的上表面和所述热固性树脂组合物（204）的上表面同时被磨损，从而形成彼此基本齐平的表面。 由于在用热固性树脂组合物（204）密封的同时磨损，因此可以减小厚度而不损坏电子元件（203）。 此外，可以防止电气元件（203）和布线图案（201）被研磨液体污染。 以这种方式，可以获得能够在保持其机械强度的同时减小其厚度的电子元件内置模块。

公开(公告)号：DE69434049T2

公开(公告)日：2005-02-10

申请号：DE69434049

申请日：1994-02-02

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： NAKAMURA YOSHIFUMI ,  BESSHO YOSHIHIRO ,  YUHAKU SATORU ,  HAKOTANI YASUHIKO ,  ITAGAKI MINEHIRO ,  MIURA KAZUHIRO

IPC: H01L21/48 ,  H05K1/03 ,  H05K1/09 ,  H05K3/40 ,  H05K3/46

Abstract: The method of manufacturing a ceramic substrate having a plurality of bumps of the present invention, includes the steps of: forming a bump forming layer having a plurality of holes therein on at least one of upper and lower faces of a laminated body of green sheets; filling the holes in the bump forming layer with a bump forming paste; sintering the laminated body of the green sheets and the bump forming layer; and forming bumps made of the sintered bump forming paste by removing the bump forming layer.

公开(公告)号：DE69434049D1

公开(公告)日：2004-11-11

申请号：DE69434049

申请日：1994-02-02

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： NAKAMURA YOSHIFUMI ,  BESSHO YOSHIHIRO ,  YUHAKU SATORU ,  HAKOTANI YASUHIKO ,  ITAGAKI MINEHIRO ,  MIURA KAZUHIRO

IPC: H01L21/48 ,  H05K1/03 ,  H05K1/09 ,  H05K3/40 ,  H05K3/46

Abstract: The method of manufacturing a ceramic substrate having a plurality of bumps of the present invention, includes the steps of: forming a bump forming layer having a plurality of holes therein on at least one of upper and lower faces of a laminated body of green sheets; filling the holes in the bump forming layer with a bump forming paste; sintering the laminated body of the green sheets and the bump forming layer; and forming bumps made of the sintered bump forming paste by removing the bump forming layer.

公开(公告)号：DE69718693D1

公开(公告)日：2003-03-06

申请号：DE69718693

申请日：1997-03-05

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： ONISHI KEJI ,  IWAKI HIDEKI ,  SEKI SHUN-ICHI ,  TAGUCHI YUTAKA ,  SHIRAISHI TSUKASA ,  BESSHO YOSHIHIRO ,  KAWASAKI OSAMU ,  EDA KAZUO

IPC: H03H3/08 ,  H03H9/10