Correction of loop phase shift and phase imbalance in a Cartesian transmitter, by use of dual phase shifters

    公开(公告)号:GB2469076A

    公开(公告)日:2010-10-06

    申请号:GB0905576

    申请日:2009-03-31

    Applicant: MOTOROLA INC

    Abstract: To implement phase training in a Cartesian transmitter, the phase training module 530 adjusts the Q phase shifter 546 to minimise the Q feedback signal Qfb with a test signal on the I input only and then the module 530 adjusts the I phase shifter 544 to minimise the I feedback signal Ifb with a test signal on the Q channel only, thereby effecting separate and independent phase corrections for the I and Q loops. The technique is useful in counteracting the not insubstantial IQ imbalance exhibited by local oscillator (LO) phase shifters using separate mixers for the I and Q LO signals (figure 4). The initial setting for the I phase shifter 544 during phase training may be set in accordance with the phase shift determined for the Q phase shifter (because the I and Q phase shifts will often be comparable), thereby reducing calibration time for the I phase shifter and reducing overall phase training time.

    Wireless communication unit, linearised transmitter circuit and method of linearising therein

    公开(公告)号:GB2458624A

    公开(公告)日:2009-09-30

    申请号:GB0913951

    申请日:2007-11-01

    Applicant: MOTOROLA INC

    Abstract: A wireless communication unit (300) comprises a frequency generation circuit, and a linearised transmitter (325) operably coupled to the frequency generation circuit and having a forward path for routing a signal to be transmitted; and a feedback path, operably coupled to a power amplifier (324) and the forward path for feeding back a portion of the signal to be transmitted. The feedback path and forward path form two loops in quadrature. The frequency generation circuit comprises independent phase shift elements arranged to independently phase shift the two loops in quadrature ('I' and 'Q').

    Receiver for use in wireless communications and method of operation of the receiver

    公开(公告)号:GB2437574B

    公开(公告)日:2008-06-25

    申请号:GB0608363

    申请日:2006-04-28

    Applicant: MOTOROLA INC

    Abstract: A wireless receiver (100) for receiving and demodulating a frequency modulated RF (radio frequency) signal by a direct conversion procedure, including channels (110, 112) for producing in-phase and quadrature components of a received RF signal, and a processor (123, 133) for periodically estimating an error in at least one of the in-phase and quadrature phase components and for producing a signal for adjustment of at least one of the in-phase and quadrature components to compensate for the detected error, wherein the processor is operable to apply alternatively each of a plurality of different procedures to estimate the error, the procedures including a first procedure which is applied when a signal quality value of the received RF signal is above a threshold value and a second procedure which is applied when a signal quality value of the RF received signal is not above the threshold value.

    AGC system for receiver, particularly for TETRA signals

    公开(公告)号:GB2428146A

    公开(公告)日:2007-01-17

    申请号:GB0513759

    申请日:2005-07-06

    Applicant: MOTOROLA INC

    Abstract: A receiver 100 includes rf amplifier 105, mixer 107/108, and baseband channels 115 and 117 which include analogue to digital converters 128 and 138. RMS estimator 139 receives the ADC outputs and communicates with digital agc controller 141. Digital signal processor 140 receives the ADC outputs and calculates (161, fig.2) a peak to average ratio (PAR) of the ADC signals. An algorithm (fig.2, 163; fig.3) in the DSP140 receives PAR and RSSI estimates and establishes whether an unwanted out of band signal which may have activated the AGC is due to an interfering TETRA II (TEDS) signal. The algorithm sends an appropriate AGC threshold value to digital AGC controller 141. The AGC system overcomes problems that arise when there signals of different types, e.g. TETRA I and TETRA II, in the same spectrum.

    Wireless communication unit, linearised transmitter circuit and method of linearising therein

    公开(公告)号:GB2408860B

    公开(公告)日:2006-12-20

    申请号:GB0328110

    申请日:2003-12-04

    Applicant: MOTOROLA INC

    Abstract: A wireless communication unit (300) comprises a linearised transmitter (325, 500) having a power amplifier (324), a forward path and a feedback path for feeding back a portion of a signal to be transmitted, wherein the feedback path and forward path form two loops in quadrature. A processor (322) applies one or more training signals to a first quadrature circuit loop and a second quadrature circuit loop and measures a quadrature imbalance between the first and second quadrature circuit loops. In response the processor adjusts at least one parameter setting of a loop adjustment function (442) to balance the quadrature circuit loops. A linearised transmitter and method of training are also described. The measuring and compensating for any loop imbalance between 'I' and 'Q' paths around a feedback path provides improved accuracy and stability in phase and/or amplitude.

    Direct conversion FM receiver employing average DC offset correction

    公开(公告)号:GB2424326A

    公开(公告)日:2006-09-20

    申请号:GB0505493

    申请日:2005-03-18

    Applicant: MOTOROLA INC

    Abstract: A receiver 200 for receiving and demodulating a frequency modulated RF signal by a direct conversion procedure includes an input signal path (101) receiving an RF input signal (x(t)), an I-channel (103) including a first mixer 107 for mixing the RF input signal with an in-phase reference signal to produce an in-phase component (I(t)), a Q-channel 105 including a second mixer 109 for mixing the input signal with a quadrature-phase reference signal to produce a quadrature-phase component (Q(t)). The receiver further includes a compensator for repeatedly measuring and compensating for DC offset produced by the receiver and combined with the input signal component in a respective I and/or Q channel. The compensator estimates 202, 204 a component of the DC offset present in the respective channel (I, Q) by (i) taking a set of N samples of the value of the input signal component in the respective channel; (ii) summing the values obtained for the N samples; and (iii) calculating an average value by dividing the sum by the number N of samples, and a combiner 206, 207 operable to combine with the input signal component an adjustment signal which cancels the estimated DC noise component in the respective channel. The receiver may also include a controller 203 operably coupled to the estimator 202, 205 to provide control signals to indicate when the estimator of the compensator should release the noise value it has estimated. The controller may also indicate an integration time to be used by the estimator of each compensator. The controller may include a detector which assists in control of the estimators by determining a frequency offset between the carrier frequency of the input signal and the reference signal produced by a local oscillator 221. The controller may, via a frequency setter 222, adaptively adjust the reference frequency produced by the local oscillator.

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