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    22.
    发明专利
    未知

    公开(公告)号：BR9007841A

    公开(公告)日：1992-09-08

    申请号：BR9007841

    申请日：1990-11-27

    Applicant: MOTOROLA INC

    Inventor： BERKEN JAMES J ,  FREEBURG THOMAS A ,  OGASAWARA ROY T ,  WHITE RICHARD E ,  MITZLAFF JAMES E ,  BEDLEK GREGORY J

    IPC: H04B7/24 ,  H04J3/00 ,  H04J3/16 ,  H04L12/28 ,  H04L12/56 ,  H04B1/38 ,  H04J3/24

    Abstract: A wireless in-building telecommunications system for voice and data communications is disclosed having at least one node (101) arranged for linking to the PSTN (151) and at least one digital information source (153, 155, 157, 159) multiplicity of user modules (103) (UM's) linked to the node via a shared RF communications path (107). Each UM is coupled to a voice telephone instrument (127) and to one or more data terminals (165). The UM's communicate with the node by exchanging fast packets via the common RF path (107). The node also includes a fast-packet-switched mechanism controlled by a bandwidth allocating scheme to prevent collisions of packets as they are transmitted between the various units (101, 103) (nodes and/or user modules) that may be accessing the RF path (107). Also disclosed is a method for allocating the required bandwidth to each of the users of the common communications path in a wireless in-building telephone system. The invention provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. It also synchronizes the transfer of the data and the allocation of bus bandwidth.

    PROCESS FOR HAND-MADE PACKING
    25.
    发明专利
    PROCESS FOR HAND-MADE PACKING 未知

    公开(公告)号：HU908029D0

    公开(公告)日：1991-06-28

    申请号：HU802990

    申请日：1990-12-03

    Applicant: MOTOROLA INC

    Inventor： FREEBURG THOMAS A ,  KACZMARCZYK JOHN M ,  NOLAN MICHAEL P ,  BUCHHOLZ DALE R ,  WHITE RICHARD E ,  CHANG HUNGKUN J

    IPC: H04L12/54

    Abstract: In this invention a hierarchical addressing technique is employed in a packet communications system to enhance flexibility in handling packet information. This method permits packet message data (Fig. 3) and certain packet control data (Fig. 3) to be stored in memory locations (32, 34) without having to be duplicated at a different memory location prior to transmission of the packet. This method is preferably employed in a ring configuration in which a series of packets have addressing mechanisms which points sequentially to each other to form a ring of packets.

    PACKET/FAST PACKET SWITCH FOR VOICE AND DATA
    27.
    发明专利
    PACKET/FAST PACKET SWITCH FOR VOICE AND DATA 未知

    公开(公告)号：CA2038952C

    公开(公告)日：1998-02-03

    申请号：CA2038952

    申请日：1990-08-23

    Applicant: MOTOROLA INC

    Inventor： BUCHHOLZ DALE R ,  WHITE RICHARD E ,  JOHANSON LISA B ,  FREEBURG THOMAS A

    IPC: H04L12/64 ,  H04Q3/42 ,  H04L12/56

    Abstract: An improved network interface architecture for a packet/fast packet switch is described. This network interface architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (NI) provides a means (the NI-Bus) of passing all packets through the Network interface or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The network interface architecture, according to the invention, allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as, for example, 40 Mbps. It also allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth, through the use of the NI Base Registers.

    Packet/fast packet switch for voice and data
    28.
    发明专利
    Packet/fast packet switch for voice and data 未知

    公开(公告)号：HK99597A

    公开(公告)日：1997-08-08

    申请号：HK99597

    申请日：1997-06-26

    Applicant: MOTOROLA INC

    Inventor： WHITE RICHARD E ,  BUCHHOLZ DALE R ,  JOHANSON LISA B ,  FREEBURG THOMAS A

    IPC: H04L12/64 ,  H04J3/26

    Abstract: A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.

    30.
    发明专利
    未知

    公开(公告)号：DK0446335T3

    公开(公告)日：1995-02-27

    申请号：DK90915014

    申请日：1990-08-23

    Applicant: MOTOROLA INC

    Inventor： WHITE RICHARD E ,  BUCHHOLZ DALE R ,  FREEBURG THOMAS A ,  JOHANSON LISA B

    IPC: H04L12/64 ,  H04J3/26

    Abstract: A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.

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