公开(公告)号：US11733896B2

公开(公告)日：2023-08-22

申请号：US17744563

申请日：2022-05-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vamsi Pavan Rayaprolu ,  Shane Nowell ,  Michael Sheperek

IPC: G06F3/06 ,  G11C16/04

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0483

Abstract: A system can include a memory device and a processing device to perform operations that include performing, at a first frequency, a calibration scan, where the calibration scan includes calibrating block family-to-bin associations for one or more younger voltage bins based on first measurement data determined by the calibration scan, and calibrating block family-to-bin associations for one or more older voltage bins based on second measurement data provided by a media management scan, where the media management scan is performed at a second frequency, such that the second frequency is lower than the first frequency, each of the younger voltage bins satisfies a first age threshold criterion, and each of the older voltage bins satisfies a second age threshold criterion.

公开(公告)号：US11726867B2

公开(公告)日：2023-08-15

申请号：US17741940

申请日：2022-05-11

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Xiangang Luo ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe

IPC: G06F11/10 ,  G06F11/00 ,  G06F11/14

CPC classification number: G06F11/1048 ,  G06F11/108 ,  G06F11/1044 ,  G06F11/1441

Abstract: A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.

公开(公告)号：US20230230645A1

公开(公告)日：2023-07-20

申请号：US18125595

申请日：2023-03-23

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore K. Muchherla

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/16 ,  G06F12/0891 ,  G11C16/26

CPC classification number: G11C16/3495 ,  G11C16/102 ,  G11C16/16 ,  G06F12/0891 ,  G11C16/26 ,  G06F2212/7211 ,  G06F2212/7201 ,  G06F2212/1016

Abstract: A method includes determining that a ratio of valid data portions to a total quantity of data portions of a block of memory cells is greater than or less than a valid data portion threshold and determining that health characteristics for the valid data portions of the block of memory cells are greater than or less than a valid data health characteristic threshold. The method further includes performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is greater than the valid data portion threshold and performing a second media management operation on at least a portion of the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is less than the valid data portion threshold and the health characteristics for the valid data portions are greater than the valid data health characteristic threshold.

公开(公告)号：US11567665B2

公开(公告)日：2023-01-31

申请号：US17007538

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore K. Muchherla

IPC: G06F3/06

Abstract: A method includes determining a respective number of and respective locations of valid data portions of a plurality of blocks of NAND memory cells, based on the respective locations of the valid data portions, determining respective dispersions of the valid data portions within the plurality of blocks of NAND memory cells, based at least on the respective dispersions, selecting a block of NAND memory cells from the plurality of blocks of NAND memory cells, and performing a folding operation on the selected block.

公开(公告)号：US11557357B2

公开(公告)日：2023-01-17

申请号：US17014583

申请日：2020-09-08

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Vamsi Pavan Rayaprolu ,  Larry J. Koudele

IPC: G11C7/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/32 ,  G11C16/26

Abstract: An example memory sub-system to receive a request to execute a read operation associated with data of a memory unit of a memory sub-system. A time after program associated with the data is determined. The time after program is compared to a threshold time level to determine if a first condition is satisfied or a second condition is satisfied. The memory sub-system selects one of a first set of read offset values based on the time after program in response to satisfying the first condition, or a second set of read offset values based on a data state metric measurement in response to satisfying the second condition.

公开(公告)号：US11527294B2

公开(公告)日：2022-12-13

申请号：US17001769

申请日：2020-08-25

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Karl D. Schuh ,  Jeffrey S. McNeil, Jr. ,  Kishore K. Muchherla ,  Ashutosh Malshe ,  Jiangang Wu

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/14 ,  G11C29/10 ,  G06F12/02 ,  G11C16/26

Abstract: A system includes a memory device including a plurality of groups of memory cells and a processing device that is operatively coupled to the memory device. The processing device is to receive a request to determine a reliability of the plurality of groups of memory cells. The processing device is further to perform, in response to receipt of the request, a scan operation on a sample portion of the plurality of groups of memory cells to determine a reliability of the sample portion that is representative of the reliability of the plurality of groups of memory cells.

公开(公告)号：US11495309B2

公开(公告)日：2022-11-08

申请号：US17123997

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Christopher M. Smitchger

IPC: G11C7/22 ,  G11C16/34 ,  G11C16/24 ,  G11C16/10 ,  G11C16/04 ,  G11C16/26

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including determining a voltage distribution metric associated with a at least part of a block of the memory device; determining a threshold value for the voltage distribution metric associated with the block; and responsive to determining that the voltage distribution metric exceeds the threshold value, performing a media management operation with respect to the block.

公开(公告)号：US20220351796A1

公开(公告)日：2022-11-03

申请号：US17867538

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Renato C. Padilla ,  Sampath K. Ratnam ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Gary F. Besinga ,  Michael G. Miller ,  Tawalin Opastrakoon

IPC: G11C29/10 ,  G06F11/07

Abstract: A method includes associating each block of a plurality of blocks of a memory device with a corresponding frequency access group of a plurality of frequency access groups based on corresponding access frequencies, and performing scan operations on blocks of each of the plurality of frequency access groups using a scan frequency that is different from scan frequencies of other frequency access groups. A scan operation performed on a frequency access group with a higher access frequency uses a higher scan frequency than a scan operation performed on a frequency access group with a lower access frequency.

公开(公告)号：US11450392B2

公开(公告)日：2022-09-20

申请号：US16718051

申请日：2019-12-17

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Harish R. Singidi ,  Renato C. Padilla ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe ,  Sampath K. Ratnam

IPC: G11C16/08 ,  G11C16/34 ,  G06F11/30 ,  G06F11/07

Abstract: A processing device in a memory system maintains a counter to track a number of read operations performed on a data block of a memory device and determines that the number of read operations performed on the data block satisfies a first threshold criterion. The processing device further determines whether a number of scan operations performed on the data block satisfies a scan threshold criterion. Responsive to the number of scan operations performed on the data block satisfying the scan threshold criterion, the processing device performs a first data integrity scan to determine one or more first error rates for the data block, each of the one or more first error rates corresponding to a first set of wordlines of the data block, the first set comprising first alternating pairs of adjacent wordlines.

公开(公告)号：US11436085B2

公开(公告)日：2022-09-06

申请号：US17112786

申请日：2020-12-04

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Harish R. Singidi ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Sampath K. Ratnam

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07 ,  G06F9/50 ,  G06F12/02 ,  G06F11/30

Abstract: Write operations are performed to write data to user blocks of the memory device and to write, to a first set of purposed blocks, purposed data related to the first data written at the memory device. Whether the first set of purposed blocks satisfy a condition indicating an endurance state of the first set of purposed blocks is determined. Responsive to the first set of purposed blocks satisfies the condition, one or more blocks from a pool of storage area blocks of the memory device are allocated to a second set of purposed blocks.