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    MULTIPLE WRITE PROGRAMMING FOR A SEGMENT OF A MEMORY DEVICE
    3.
    发明申请
    MULTIPLE WRITE PROGRAMMING FOR A SEGMENT OF A MEMORY DEVICE 有权

    公开(公告)号：US20250077416A1

    公开(公告)日：2025-03-06

    申请号：US18781838

    申请日：2024-07-23

    Applicant: Micron Technology, Inc.

    Inventor： Huai-Yuan Tseng ,  Xiangyu Tang ,  Eric N. Lee ,  Haibo Li ,  Kishore Kumar Muchherla ,  Akira Goda

    IPC: G06F12/02

    Abstract: A memory device can include a memory array including memory cells arranged in one or more pages. The memory array can be coupled to control logic to receive a first request to write first data to a page of the one or more pages and program the first data to the page of the one or more pages at a first time responsive to receiving the first request. The control logic is further to receive a second request to write second data to the page of the one or more pages, read the page of the one or more pages, and program the second data to the page of the one or more pages at a second time responsive to receiving the second request. The control logic can also receive an erase request to erase the one or more pages after the second time.

    Memory devices for multiple read operations
    4.
    发明授权
    Memory devices for multiple read operations 有权

    公开(公告)号：US12142343B2

    公开(公告)日：2024-11-12

    申请号：US18232949

    申请日：2023-08-11

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Eric N. Lee ,  Kishore Kumar Muchherla ,  Jeffrey S. McNeil ,  Jung-Sheng Hoei

    IPC: G11C16/06 ,  G11C7/10 ,  G11C7/14 ,  G11C7/22

    Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.

    WORKLOAD-BASED SCAN OPTIMIZATION
    8.
    发明公开
    WORKLOAD-BASED SCAN OPTIMIZATION 审中-公开

    公开(公告)号：US20240248646A1

    公开(公告)日：2024-07-25

    申请号：US18623881

    申请日：2024-04-01

    Applicant: Micron Technology, Inc.

    Inventor： Kishore Kumar Muchherla ,  Eric N. Lee ,  Jeffrey S. McNeil ,  Jonathan S. Parry ,  Lakshmi Kalpana Vakati

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679

    Abstract: A method performed by a processing device receives a plurality of write operation requests, where each of the write operation requests specifies a respective one of the memory units, identifies one or more operating characteristic values, where each operating characteristic value reflects one or more memory access operations performed on a memory device, and determines whether the operating characteristic values satisfy one or more threshold criteria. Responsive to determining that the operating characteristic values satisfy the one or more threshold criteria, the method performs a plurality of write operations, where each of the write operations writes data to the respective one of the memory units, and performs a multiple-read scan operation subsequent to the plurality of write operations, where the multiple-read scan operation reads data from each of the memory units.

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