公开(公告)号：US12217824B2

公开(公告)日：2025-02-04

申请号：US18160292

申请日：2023-01-26

Applicant: Micron Technology, Inc.

Inventor： Edmund Gieske ,  Amitava Majumdar ,  Cagdas Dirik ,  Sujeet Ayyapureddi ,  Yang Lu ,  Ameen D. Akel ,  Danilo Caraccio ,  Niccolo′ Izzo ,  Elliott C. Cooper-Balis ,  Markus H. Geiger

IPC: G11C29/52 ,  G11C7/22 ,  G11C7/24

Abstract: Systems and methods for finite time counting period counting of infinite data streams is presented. In particular example systems and methods enable counting row accesses to a memory media device over predetermined time intervals in order to deterministically detect row hammer attacks on the memory media device. Example embodiments use two identical tables that are reset at times offset in relation to each other in a ping-pong manner in order to ensure that there exists no false negative detections. The counting techniques described in this disclosure can be used in various types of row hammer mitigation techniques and can be implemented in content addressable memory or another type of memory. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be a dynamic random access memory type device.

公开(公告)号：US12182413B2

公开(公告)日：2024-12-31

申请号：US17897813

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Yang Lu ,  Edmund Gieske ,  Cagdas Dirik ,  Ameen D. Akel ,  Elliott C. Cooper-Balis ,  Amitava Majumdar ,  Danilo Caraccio ,  Robert M. Walker

IPC: G06F11/07 ,  G06F3/06

Abstract: Systems and methods for area-efficient mitigation of errors that are caused by row hammer attacks and the like in a memory media device are described. The counters for counting row accesses are maintained in a content addressable memory (CAM) the provides fast access times. The detection of errors is deterministically performed while maintaining a number of row access counters that is smaller than the total number of rows protected in the memory media device. The circuitry for the detection and mitigation may be in the memory media device or in a memory controller to which the memory media device attaches. The memory media device may be dynamic random access memory (DRAM).

公开(公告)号：US20240371449A1

公开(公告)日：2024-11-07

申请号：US18635946

申请日：2024-04-15

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Yang Lu

IPC: G11C16/34

Abstract: Apparatuses and techniques for implementing usage-based disturbance mitigation counter control are described. In some examples, a mitigation counter controller manages mitigation of usage-based disturbances by mitigating one or more wordlines in a memory device that have been disturbed. The mitigation counter controller may access a usage-based disturbance counter by activating a single sub wordline driver in the wordline, where the usage-based disturbance counter is associated with usage-based disturbances of the wordline. Activation of a single sub wordline driver to access the usage-based disturbance counter may reduce power consumption and may simplify the design of the memory device.

公开(公告)号：US12131768B2

公开(公告)日：2024-10-29

申请号：US17896337

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Yang Lu

IPC: G11C11/406 ,  G11C11/4078 ,  G11C11/408

CPC classification number: G11C11/40618 ,  G11C11/40615 ,  G11C11/4078 ,  G11C11/4085

Abstract: Systems and methods for multi-wordline direct refresh operations in response to a row hammer error in a memory bank. The approach includes detecting, by a row hammer mitigation component, a row hammer error in a memory bank; and then triggering, by the row hammer mitigation component, a response to the row hammer error. Further, a memory controller receives, from a mode register, data, based on an aliasing row counter policy, selecting a type of multi-wordline direct refresh operation to be performed on a plurality of victim memory rows within the memory bank, wherein the plurality of victim memory rows are dispersed across a plurality of memory sub-banks. The approach includes concurrently executing the selected multi-wordline direct refresh operation to the plurality of victim memory rows.

公开(公告)号：US20240339152A1

公开(公告)日：2024-10-10

申请号：US18627960

申请日：2024-04-05

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Kang-Yong Kim ,  Wonjun Choi

IPC: G11C11/4091 ,  G11C11/4078 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C11/4078 ,  G11C11/4096

Abstract: Apparatuses and techniques for implementing a data sense amplifier circuit with a hybrid architecture. With the hybrid architecture, the data sense amplifier circuit includes a first set of amplifiers that are shared by multiple banks and includes a second set of amplifiers with multiple subsets dedicated to different banks. The bank-shared amplifiers support memory operations (e.g., a read operation) across multiple banks. Each amplifier within the first set of amplifiers is coupled to at least two banks. The bank-specific amplifiers support usage-based disturbance mitigation for a corresponding bank. Each amplifier within the second set of amplifiers is coupled to one of the multiple banks. The bank-shared amplifiers enable the data sense amplifier circuit to have a smaller footprint while the bank-specific amplifiers enable the data sense amplifier circuit to support usage-based disturbance mitigation and avoid conflicts associated with some sequences of commands.

公开(公告)号：US20240321329A1

公开(公告)日：2024-09-26

申请号：US18680550

申请日：2024-05-31

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Kang-Yong Kim

IPC: G11C7/10 ,  G11C29/46

CPC classification number: G11C7/1063 ,  G11C7/1066 ,  G11C7/1096 ,  G11C29/46

Abstract: Methods, systems, and devices for selective access for grouped memory dies are described. A memory device may be configured with a select die access protocol for a group of memory dies that share a same channel. The protocol may be enabled by one or more commands from the host device, which may be communicated to each of the memory dies of the group via the channel. The command(s) may indicate a first set of one or more memory dies of the group for which a set of commands may be enabled and may also indicate a second set of one or more memory dies of the group for which at least a subset of the set of commands is disabled. When the select die access mode is enabled, the disabled memory dies may be restricted from performing the subset of commands received via the channel.

公开(公告)号：US20240177745A1

公开(公告)日：2024-05-30

申请号：US18520189

申请日：2023-11-27

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Yuan He ,  Kang-Yong Kim

IPC: G11C7/08 ,  G11C7/10 ,  G11C29/52

CPC classification number: G11C7/08 ,  G11C7/1069 ,  G11C29/52

Abstract: Apparatuses and techniques for implementing shareable usage-based disturbance circuitry are described. Shareable usage-based disturbance circuitry includes circuits (e.g., shared circuits) that manage usage-based disturbance across at least two sections of a bank of memory within a die of a memory device. In example implementations, the shareable usage-based disturbance circuitry includes a counter circuit and/or an error-correction-code circuit that is coupled to sense amplifiers associated with two neighboring sections. With the shareable usage-based disturbance circuitry, dies within the memory device can be cheaper to manufacture, can consume less power, and can have a smaller footprint with less complex signal routing compared to other dies with other circuits dedicated to mitigating usage-based disturbance within each section.

公开(公告)号：US20240170091A1

公开(公告)日：2024-05-23

申请号：US18511440

申请日：2023-11-16

Applicant: Micron Technology, Inc.

Inventor： Yoshiro Riho ,  Hyun Yoo Lee ,  Yang Lu

IPC: G11C29/52 ,  G11C7/08 ,  G11C7/10

CPC classification number: G11C29/52 ,  G11C7/08 ,  G11C7/1039

Abstract: Described apparatuses and methods provide system error correction code (ECC) circuitry routing that segregates even sense amp (SA) line data sets and odd SA line data sets in a memory, such as a low-power dynamic random-access memory. A memory device may include one or more dies, and a die can have even SA line data sets and odd SA line data sets. The memory device may also include ECC circuitry comprising one or more ECC engines. By segregating the data sets, instead of coupling even and odd SA line data sets to a single ECC engine, double-bit errors on a single word line may be separated into two single-bit errors. Thus, by utilizing system ECC circuitry routing in this way, even a one-bit ECC algorithm may be used to correct double bits, which may increase data reliability.

公开(公告)号：US20240079036A1

公开(公告)日：2024-03-07

申请号：US17930034

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Mark Kalei Hadrick ,  Kang-Yong Kim

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/023 ,  G06F13/1668 ,  G06F2212/1016

Abstract: Apparatuses and techniques for implementing a standalone mode are described. The standalone mode refers to a mode in which a die that is designed to operate as one of multiple dies that are interconnected can operate independently of another one of the multiple dies. Prior to connecting the die to the other die, the die can perform a standalone read operation and/or a standalone write operation in accordance with the standalone mode. In this way, testing (or debugging) can be performed during an earlier stage in the manufacturing process before integrating the die into an interconnected die architecture. For example, this type of testing can be performed at a wafer level or at a single-die-package (SDP) level. In general, the standalone mode can be executed independent of whether the die is connected to the other die.

公开(公告)号：US20240078041A1

公开(公告)日：2024-03-07

申请号：US17930044

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Kang-Yong Kim

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0614 ,  G06F3/0673 ,  G06F12/0223

Abstract: This document describes apparatuses and techniques for die-based rank management for a memory system. In various aspects, a die-based rank controller (controller) can determine which memory dies of a memory device are not functional to store data and correlate rank selections of a memory system to ranks of other memory dies (e.g., functional memory dies). The controller may store information that indicates the correlation or mapping of the rank selections to the ranks of the other memory dies to enable access to those ranks of the memory system. In some aspects, the controller receives a command to access the memory device with a rank selection, and the controller enables access to a corresponding rank based on the information. By so doing, aspects of die-based rank management enable memory packages with non-functional memory dies to be used instead of discarded, which can increase production utilization or lower manufacturing costs.